📄 sram4m.map.rpt
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; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; Total logic cells in carry chains ; 18 ;
; I/O pins ; 88 ;
; Maximum fan-out node ; res1 ;
; Maximum fan-out ; 41 ;
; Total fan-out ; 411 ;
; Average fan-out ; 2.11 ;
+---------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |sram4m ; 107 (107) ; 0 ; 0 ; 88 ; 0 ; 107 (107) ; 0 (0) ; 0 (0) ; 18 (18) ; 0 (0) ; |sram4m ; work ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; bt860_data[0]$latch ; bt860_data[6]~39 ; yes ;
; bt860_data[1]$latch ; bt860_data[6]~39 ; yes ;
; bt860_data[2]$latch ; bt860_data[6]~39 ; yes ;
; bt860_data[3]$latch ; bt860_data[6]~39 ; yes ;
; bt860_data[4]$latch ; bt860_data[6]~39 ; yes ;
; bt860_data[5]$latch ; bt860_data[6]~39 ; yes ;
; bt860_data[6]$latch ; bt860_data[6]~39 ; yes ;
; bt860_data[7]$latch ; bt860_data[6]~39 ; yes ;
; we_1$latch ; we_1~3 ; yes ;
; we_2$latch ; we_2~0 ; yes ;
; res1 ; res1~1 ; yes ;
; dio_1[0]$latch ; dio_1[0]~0 ; yes ;
; dio_1[0]_1468 ; dio_1[0]~0 ; yes ;
; dio_1[1]$latch ; dio_1[0]~0 ; yes ;
; dio_1[2]$latch ; dio_1[0]~0 ; yes ;
; dio_1[3]$latch ; dio_1[0]~0 ; yes ;
; dio_1[4]$latch ; dio_1[0]~0 ; yes ;
; dio_1[5]$latch ; dio_1[0]~0 ; yes ;
; dio_1[6]$latch ; dio_1[0]~0 ; yes ;
; dio_1[7]$latch ; dio_1[0]~0 ; yes ;
; dio_2[0]$latch ; dio_2[0]~2 ; yes ;
; dio_2[0]_1046 ; dio_2[0]~2 ; yes ;
; dio_2[1]$latch ; dio_2[0]~2 ; yes ;
; dio_2[2]$latch ; dio_2[0]~2 ; yes ;
; dio_2[3]$latch ; dio_2[0]~2 ; yes ;
; dio_2[4]$latch ; dio_2[0]~2 ; yes ;
; dio_2[5]$latch ; dio_2[0]~2 ; yes ;
; dio_2[6]$latch ; dio_2[0]~2 ; yes ;
; dio_2[7]$latch ; dio_2[0]~2 ; yes ;
; Number of user-specified and inferred latches = 29 ; ; ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; No ; |sram4m|bt860_data[0]~6 ;
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |sram4m|addr1[11]~0 ;
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |sram4m|addr1[6]~29 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Mon Oct 20 16:40:22 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sram4m -c sram4m
Info: Found 2 design units, including 1 entities, in source file sram4m.vhd
Info: Found design unit 1: sram4m-rtl
Info: Found entity 1: sram4m
Warning: Can't analyze file -- file D:/aaa/aaa.vhd is missing
Warning: Can't analyze file -- file D:/sram4m/sram4m.bdf is missing
Info: Elaborating entity "sram4m" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at sram4m.vhd(42): signal "bt835_vactive" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(46): signal "bt835_data" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(50): signal "dio_1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(65): signal "bt835_vactive" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(69): signal "bt835_data" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(73): signal "dio_2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at sram4m.vhd(37): inferring latch(es) for signal or variable "cs_1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at sram4m.vhd(37): inferring latch(es) for signal or variable "res1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at sram4m.vhd(37): inferring latch(es) for signal or variable "we_1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at sram4m.vhd(37): inferring latch(es) for signal or variable "dio_1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at sram4m.vhd(37): inferring latch(es) for signal or variable "oe_1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at sram4m.vhd(37): inferring latch(es) for signal or variable "bt860_data", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at sram4m.vhd(37): inferring latch(es) for signal or variable "cs_2", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at sram4m.vhd(37): inferring latch(es) for signal or variable "res2", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at sram4m.vhd(37): inferring latch(es) for signal or variable "we_2", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at sram4m.vhd(37): inferring latch(es) for signal or variable "dio_2", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at sram4m.vhd(37): inferring latch(es) for signal or variable "oe_2", which holds its previous value in one or more paths through the process
Warning (10492): VHDL Process Statement warning at sram4m.vhd(87): signal "addr1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(89): signal "addr1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(91): signal "addr1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(94): signal "addr1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(96): signal "addr1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(97): signal "addr1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(101): signal "addr1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(109): signal "addr1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(111): signal "addr1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(113): signal "addr1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(114): signal "bt835_vreset" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(116): signal "addr1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(118): signal "addr1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(119): signal "addr1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(123): signal "addr1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(131): signal "addr2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(134): signal "addr2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(135): signal "addr2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(136): signal "addr2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(138): signal "addr2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(142): signal "addr2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(149): signal "addr2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at sram4m.vhd(127): inferring latch(es) for signal or variable "addr2", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at sram4m.vhd(127): inferring latch(es) for signal or variable "adr_2", which holds its previous value in one or more paths through the process
Warning (10492): VHDL Process Statement warning at sram4m.vhd(157): signal "addr2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(159): signal "addr2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(161): signal "addr2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(162): signal "bt835_vreset" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(164): signal "addr2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(166): signal "addr2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(167): signal "addr2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at sram4m.vhd(171): signal "addr2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10034): Output port "flash_cle" at sram4m.vhd(5) has no driver
Warning (10034): Output port "flash_ale" at sram4m.vhd(6) has no driver
Warning (10034): Output port "flash_ce" at sram4m.vhd(7) has no driver
Warning (10034): Output port "flash_we" at sram4m.vhd(8) has no driver
Warning (10034): Output port "flash_re" at sram4m.vhd(9) has no driver
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