sram4m.vhd

Altera cyclone ep1c6对sram idt71系列的读写时序控制

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sram4m IS
	PORT(	flash_cle		:OUT STD_LOGIC;						
			flash_ale		:OUT STD_LOGIC;						
			flash_ce		:OUT STD_LOGIC;							
			flash_we		:OUT STD_LOGIC;							
			flash_re		:OUT STD_LOGIC;							
			flash_wp		:OUT STD_LOGIC;							
			bt835_field		:IN STD_LOGIC;
			bt835_hreset	:IN STD_LOGIC;							--bt835
			bt835_vreset	:IN STD_LOGIC;							--bt835
			bt835_hactive	:IN STD_LOGIC;							--bt835,行有效
			bt835_vactive	:IN STD_LOGIC;							--bt835,场有效
			bt835_clk2		:IN STD_LOGIC;							--bt835,时钟
			bt835_data		:IN STD_LOGIC_VECTOR(15 DOWNTO 8);		--bt835,data
			bt860_data		:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);		--bt860,data
			dio_1			:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);	--数据进出1			
			dio_2			:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);	--数据进出2		
			cs_1			:OUT STD_LOGIC;							--片选1
			we_1			:OUT STD_LOGIC	:='0';					--写使能1,0 is vaild
			oe_1			:OUT STD_LOGIC	:='0';					--读使能1,0 is vaild
			we_2			:OUT STD_LOGIC	:='0';					--写使能2
			oe_2			:OUT STD_LOGIC	:='0';					--读使能2
			cs_2			:OUT STD_LOGIC;							--片选2
			adr_1			:OUT STD_LOGIC_VECTOR(18 DOWNTO 0);		--19位地址1
			adr_2			:OUT STD_LOGIC_VECTOR(18 DOWNTO 0));	--19位地址2
END sram4m;

ARCHITECTURE rtl OF sram4m IS
	SIGNAL addr1		:STD_LOGIC_VECTOR(18 DOWNTO 0);
	SIGNAL addr2		:STD_LOGIC_VECTOR(18 DOWNTO 0);
	SIGNAL res1			:STD_LOGIC	:='1';							--reset1
	SIGNAL res2			:STD_LOGIC	:='1';							--reset2
BEGIN													--sram--	
	PROCESS(bt835_field,bt835_vreset,bt835_hreset,bt835_hactive)
	BEGIN
		IF (bt835_field='1') THEN				--奇场
			cs_1<='0';
			IF (bt835_vreset='1') THEN
				IF(bt835_vactive='0')THEN
					res1<='1';
					IF (bt835_hreset='1' AND bt835_hactive='1') THEN	--datain
						we_1<='0';
						dio_1(7 DOWNTO 0)<=bt835_data(15 DOWNTO 8);				
					ELSIF (bt835_hreset='0' OR bt835_hactive='0') THEN	--dataout
						we_1<='1';
						oe_1<='0';							
						bt860_data(7 DOWNTO 0)<=dio_1(7 DOWNTO 0);
						res1<='0';
					END IF;
					--res1<='0';
				END IF;
					--res1<='0';
				ELSE												--高阻态
				dio_1<="ZZZZZZZZ";
				--res1<='0';
			END IF;
		END IF;
		
		IF (bt835_field='0') THEN
			cs_2<='0';
			IF (bt835_vreset='1') THEN
				IF(bt835_vactive='0')THEN
					res2<='1';
					IF (bt835_hreset='1' AND bt835_hactive='1') THEN	--datain
						we_2<='0';	
						dio_2(7 DOWNTO 0)<=bt835_data(15 DOWNTO 8);				
					ELSIF (bt835_hreset='0' OR bt835_hactive='0') THEN--dataout
						we_2<='1';
						oe_2<='0';
						bt860_data(7 DOWNTO 0)<=dio_2(7 DOWNTO 0);
					END IF;				
					res2<='0';	
				END IF;
			ELSE												--高阻态
				dio_2<="ZZZZZZZZ";
			END IF;
		END IF;
	END PROCESS;

	PROCESS (res1,bt835_clk2,bt835_hreset,bt835_vreset)			--产生sram1列地址
		BEGIN
			IF (res1 ='0' ) THEN
				addr1(9 DOWNTO 0)<="0000000000";
				adr_1(9 DOWNTO 0)<=addr1(9 DOWNTO 0);
			ELSIF (bt835_clk2='1') THEN
				IF(addr1(9 DOWNTO 0)="1111000000" AND bt835_hreset='1') THEN
					addr1(9 DOWNTO 0)<="1111000000";
					adr_1(9 DOWNTO 0)<=addr1(9 DOWNTO 0);
				ELSIF (bt835_hreset='0') THEN
					addr1(9 DOWNTO 0)<="0000000000";
					adr_1(9 DOWNTO 0)<=addr1(9 DOWNTO 0);
				ELSE
					addr1(9 DOWNTO 0)<=addr1(9 DOWNTO 0)+1;
					adr_1(9 DOWNTO 0)<=addr1(9 DOWNTO 0);
				END IF;
			ELSE
				addr1(9 DOWNTO 0)<="ZZZZZZZZZZ";
				adr_1(9 DOWNTO 0)<=addr1(9 DOWNTO 0);
			END IF;	
	END PROCESS;

	PROCESS (res1, bt835_hreset) 								--产生行地址
		BEGIN
			IF (res1 ='0' ) THEN
				addr1(18 DOWNTO 11)<="00000000";
				adr_1(18 DOWNTO 11)<=addr1(18 DOWNTO 11);
			ELSIF (bt835_hreset='1' ) THEN
				IF(addr1(18 DOWNTO 11)="11110000") THEN
					addr1(18 DOWNTO 11)<="11110000";
					adr_1(18 DOWNTO 11)<=addr1(18 DOWNTO 11);
				ELSIF (bt835_vreset='0' ) THEN
					addr1(18 DOWNTO 11)<="00000000";
					adr_1(18 DOWNTO 11)<=addr1(18 DOWNTO 11);
				ELSE
					addr1(18 DOWNTO 11)<=addr1(18 DOWNTO 11)+1;
					adr_1(18 DOWNTO 11)<=addr1(18 DOWNTO 11);
				END IF;
			ELSE
				addr1(18 DOWNTO 11)<="ZZZZZZZZ";
				adr_1(18 DOWNTO 11)<=addr1(18 DOWNTO 11);
			END IF;
	END PROCESS;
	
	PROCESS (res2,bt835_clk2,bt835_hreset,bt835_vreset)			--产生sram2列地址
		BEGIN
			IF (res2 ='0' ) THEN
				addr2(9 DOWNTO 0)<="0000000000";
				adr_2(9 DOWNTO 0)<=addr2(9 DOWNTO 0);
			ELSIF (bt835_clk2='1' ) THEN
				IF(bt835_hreset='1' )THEN
					addr2(9 DOWNTO 0)<=addr2(9 DOWNTO 0)+1;
					adr_2(9 DOWNTO 0)<=addr2(9 DOWNTO 0);
					IF( addr2(9 DOWNTO 0)="1111000000" ) THEN
						addr2(9 DOWNTO 0)<="1111000000";
						adr_2(9 DOWNTO 0)<=addr2(9 DOWNTO 0);
					END IF;
				ELSIF (bt835_hreset='0' OR bt835_vreset='0' ) THEN
					addr2(9 DOWNTO 0)<="0000000000";
					adr_2(9 DOWNTO 0)<=addr2(9 DOWNTO 0);
				--ELSE
				--	addr2(9 DOWNTO 0)<=addr2(9 DOWNTO 0)+1;
				--	adr_2(9 DOWNTO 0)<=addr2(9 DOWNTO 0);
				END IF;
			ELSE
				addr2(9 DOWNTO 0)<="ZZZZZZZZZZ";
				adr_2(9 DOWNTO 0)<=addr2(9 DOWNTO 0);
			END IF;
	END PROCESS;

	PROCESS (res2, bt835_hreset) 								--产生行地址
		BEGIN
			IF (res2 ='0' ) THEN
				addr2(18 DOWNTO 11)<="00000000";
				adr_2(18 DOWNTO 11)<=addr2(18 DOWNTO 11);
			ELSIF (bt835_hreset='1' ) THEN
				IF(addr2(18 DOWNTO 11)="11110000") THEN
					addr2(18 DOWNTO 11)<="11110000";
					adr_2(18 DOWNTO 11)<=addr2(18 DOWNTO 11);
				ELSIF (bt835_vreset='0' ) THEN
					addr2(18 DOWNTO 11)<="00000000";
					adr_2(18 DOWNTO 11)<=addr2(18 DOWNTO 11);
				ELSE
					addr2(18 DOWNTO 11)<=addr2(18 DOWNTO 11)+1;
					adr_2(18 DOWNTO 11)<=addr2(18 DOWNTO 11);
				END IF;
			ELSE
				addr2(18 DOWNTO 11)<="ZZZZZZZZ";
				adr_2(18 DOWNTO 11)<=addr2(18 DOWNTO 11);
			END IF;			
	END PROCESS;
END rtl;