uart_top.v.bak

实现FPGA与PC机的串口通信功能

/******************************************************************************
* File:    uart_tb.v
* Version: V0.0
* Author:  minjingguo <[e-mail]>
* Date:    20070816
* Company: SHHIC Co., Ltd.
******************************************************************************
* Description:
* to transmit 8 bits and receive 8 bits for one cycle time
*
******************************************************************************
* Version: V0.1
* Modifier: name <email>
* Date:
* Description: the signal clk16x is needed to gobal time constrait
******************************************************************************/

// *************************
// INCLUDES
// ************************* 


// *************************    
// MODULE DEFINTION
//**************************

module  uart
    (
    //INPUTS
    wr      ,   //the wr=1 width > one cycle of clk, to start transmit
    rst     ,   //rst = 0 for reset module
    clk     ,   //input clock
    rd      ,   //the rd=1 width > one cycle of clk, to start receive
    rxd     ,   //the data receive from the wire     
    data_in ,   //the data for transmit
    parity_def, //the parity pre-define,0 or 1
    //OUTPUTS
    int     ,   
    txd     ,   //the transmit wire
    dat_rdy ,   //when dat_rdy = 0 for receive is idle
    tbre    ,   //when tbre = 0 for transmit is idle
    framing_error,//framing_error default value = 0
    parity_error,//parity_error default value =0. it is error when parity_error is not equal to framing_error,
    data_out     //the receive data
    );
    
// *************************
// INPUTS
// *************************
input           clk         ;
input           rst         ;
input           rxd         ;
input           wr,rd       ;
input           parity_def  ;

input     [7:0] data_in     ;

// *************************
// OUTPUTS 
// *************************
output          int          ;
output          txd          ;
output          dat_rdy      ;
output          tbre         ;
output          framing_error;
output          parity_error ;

output    [7:0] data_out     ;

// *************************
// INTERNAL SIGNALS
// *************************
reg     [8:0]   clkdiv_cnt   ;
reg             clk16x       ;


// **************************************************
//---------------setup baud rate---------------------
// **************************************************
always @(posedge clk or negedge rst)
begin
    if (rst== 1'h0)
       clkdiv_cnt  <= 9'b0;
    else if (clkdiv_cnt==26)         //baud rate=115.75 k   and pc's baud rate=115.2k
//     if (clkdiv_cnt==325);
       clkdiv_cnt  <= 9'b0;
    else
       clkdiv_cnt  <= clkdiv_cnt+1;
end

always @(posedge clk or negedge rst)
begin
    if (rst== 1'h0)
        clk16x  <= 1'b0;           
    else if (clkdiv_cnt==13)  //clk16x ~ 1852k
        clk16x  <= 1'b1;
    else if (clkdiv_cnt==26)
        clk16x  <= 1'b0;
end 

reg clk16x_b1;
reg	[1:0]	wr_pls,rd_pls;
always @(posedge clk) clk16x_b1 <= clk16x;
wire clk16x_nege = ~clk16x & clk16x_b1;
// **************************************************
//--------------------receive---------------------
// **************************************************
always @(posedge clk or negedge rst)
begin
    if (rst== 1'h0)
      rd_pls  <= 2'h0;
    else if (rd)
      rd_pls  <= 2'h1;
    else if (rd_pls==2'h1 && clk16x_nege)
      rd_pls  <= 2'h3;
    else if (rd_pls==2'h3 && clk16x_nege)
      rd_pls  <= 2'h0;
end

always @(posedge clk or negedge rst)
begin
    if (rst== 1'h0)
      wr_pls  <= 2'h0;
    else if (wr)
      wr_pls  <= 2'h1;
    else if (wr_pls==2'h1 && clk16x_nege)
      wr_pls  <= 2'h3;
    else if (wr_pls==2'h3 && clk16x_nege)
      wr_pls  <= 2'h0;
end  
     
//Assert interrupt if transmitting or rcving complete
reg tbre_b1, dat_rdy_b1;
always @(posedge clk) begin
    tbre_b1 <= tbre;
    dat_rdy_b1 <= dat_rdy;
end
assign int = ((~tbre & tbre_b1) || (~dat_rdy_b1 & dat_rdy));

// *************************
// SUBMODULE INSTANTIATION
// *************************
uart_tx     U_TX
    (
    //INPUT
    .rst     (rst       ),
    .clk16x  (clk16x    ),
    .din     (data_in   ),
    .wr      (wr_pls[1] ),
    .parity_def(parity_def),
    //OUTPUT
    .tbre    (tbre      ),
    .sdo     (txd       )
    );
    
uart_rx     U_RX
    (
    //INPUTS
    .rst     (rst         ),
    .clk16x  (clk16x      ),
    .rd      (rd_pls[1]   ),
    .rxd     (rxd         ),
    .parity_def(parity_def),
                        
    //OUTPUT            
    .dout    (data_out  ),
    .dat_rdy (dat_rdy   ),
    .framing_error(framing_error),
    .parity_error (parity_error )   
    );

endmodule