uart_tx.v

实现FPGA与PC机的串口通信功能

/******************************************************************************
* File:    uart_tb.v
* Version: V0.0
* Author:  minjingguo <[e-mail]>
* Date:    20070814
* Company: SHHIC Co., Ltd.
******************************************************************************
* Description:
* 
*
******************************************************************************
* Version: V0.1
* Modifier: name <email>
* Date:
* Description:
******************************************************************************/


// *************************    
// MODULE DEFINTION
//**************************

module  uart_tx
    (
    //INPUT
    rst     ,
    clk16x  ,
    din     ,
    wr      ,
    parity_def,           
    
    //OUTPUT
    tbre    ,       //tbre=0 if tx is empty
    sdo     
    );
    
// *************************
// INPUTS
// *************************
input           rst         ;
input           clk16x      ;
input   [7:0]   din         ;
input           wr          ;
input           parity_def  ;
// *************************
// OUTPUTS 
// *************************
output          tbre        ;
output          sdo         ;

// *************************
// INTERNAL SIGNALS
// *************************
reg     [3:0]   cnt_clk     ;
reg     [3:0]   cnt_byte    ;
reg             tbre        ;
reg     [7:0]   tbr         ;
reg             sdo         ;
reg     [7:0]   tsr         ;
reg		parity	;
// *************************
// CODE
// *************************

/////////////////////////////////////////////////////////////////////////////////////
//process for generate the clock numbers for transmit one byres data + verify data //
//note: one cycle for transmit needs 16 x 12 = 192 clocks                          //
///////////////////////////////////////////////////////////////////////////////////// 
always @(posedge clk16x or negedge rst)
begin
    if (rst== 1'h0)
    begin
        cnt_clk     <= 4'hf;
        cnt_byte    <= 4'hf;
    end
    else
    begin
        if (cnt_byte==4'hf)
        begin
            if (wr)
            begin
                cnt_clk     <= 4'b0;
                cnt_byte    <= 4'b0;
            end
        end
        else
        begin
            cnt_clk     <= cnt_clk+1;
            if (cnt_clk==4'hf)
            begin
                if (cnt_byte==4'hb)
                    cnt_byte    <= 4'hf;
                else
                    cnt_byte    <= cnt_byte+1;
            end
        end
    end
end

/////////////////////////////////////////////////////////////////////////////////////////
//process for generate the signal tbre                                                 //
//the signal tbre =1 during the process of transmitting data, and tbre=0 for complit   //
/////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk16x or negedge rst)
begin
    if (rst== 1'h0)
    begin
        tbre    <= 1'b0;
        tbr     <= 8'b0;
    end
    else
    begin
        if (wr)
        begin
            tbre    <= 1'b1;
            tbr     <= din;
        end
        else if (cnt_clk==4'hf && cnt_byte == 4'hb)
        begin
            tbre    <= 1'b0;
        end
    end
end

//////////////////////////////////////////////////////////////////////////////////////////
//process for generate transmit the data for serial bit                                 //
//note: the first one bit for start=0 bit, before the start bit wait for 8 clocks,      //
//      after 16 clocks for start bit, transmit 8bits data with transmit the msb firstly//
//      then parity bit, last transmit for stop bit                                     //
//////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk16x or negedge rst)
begin
    if (rst== 1'h0)
    begin
        sdo     <= 1'b1;
        parity <= 1'b1 ;
        tsr     <= 8'b0;
    end
    else if (cnt_clk==4'h7)//wait for 8 clocks
    begin
        if (cnt_byte == 4'h0)
        begin
            tsr     <= tbr;
            sdo     <= 1'b0;//set start bit for "0"
            parity  <= parity_def;
        end
        else if ((cnt_byte >= 4'h1) && (cnt_byte <= 4'h8))//wait for 16 clocks
        begin
            tsr     <= {tsr[6:0], 1'h0};//shift left one bit
            sdo     <= tsr[7] ;         //transmit the bit[7]
            parity  <= parity ^ tsr[7] ;//compute the bit for parity
        end
        else if (cnt_byte == 4'h9)//wait for 9 cycles
        begin
            sdo  <= parity ;//transmit the parity bit
        end
        else if (cnt_byte == 4'ha)
        begin
            sdo  <= 1'b0 ;//transmit the stop bit
        end
        else if (cnt_byte == 4'hb)
        begin
            sdo  <= 1'b1 ;//set transmit signal=1, after complete transmit
            parity  <= parity_def;
        end
    end
end

endmodule