tp.v

实现FPGA与PC机的串口通信功能

///////////////////////////////////////////////////////////
// File:    ucps_AES_128bit.v
// Version: V0.0
// Author:  Jim Luo <[e-mail]>
// Date:    070904
// Company: SHHIC Co., Ltd.
////////////////////////////////////////////////////////////
// Description:
// This is the AES arithmetic file.
//
////////////////////////////////////////////////////////////
// Version: V0.1
// Modifier: name <email>
// Date:
// Description:
////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

module test_aes128_tp;
    reg[31:0] data;
    wire[31:0] data_out;
    reg clk, rst;
    reg aes_enable;
    reg read_enable;
    reg data_enable;
    wire aes_out; 
    
    parameter delay=100;
    parameter divclk=10;
    parameter dclk=5;
    parameter dk=1;
    
    always # dclk clk=~clk;
    
    aes128_top aes1(.clock(clk), .read_enable(read_enable), .aes_enable(aes_enable), .data_enable(data_enable), .data(data),  
    .reset(rst), .aes_out(aes_out), .data_out(data_out));
    
    initial 
       begin                        //testbench
          clk=1'b1;
       end
       
    initial 
       begin                        //testbench
               data_enable=1'b0;
          #20  data_enable=1'b1;
          #10  data_enable=1'b0;
          #10  data_enable=1'b1;
          #10  data_enable=1'b0;
          #30  data_enable=1'b1;
          #10  data_enable=1'b0;
          #20  data_enable=1'b1;
          #10  data_enable=1'b0;
          #10  data_enable=1'b1;
          #10  data_enable=1'b0;
          #30  data_enable=1'b1;
          #10  data_enable=1'b0;
          #10  data_enable=1'b1;
          #10  data_enable=1'b0;
          #30  data_enable=1'b1;
          #10  data_enable=1'b0;//240
                   
       end 
 
initial 
       begin                        //testbench
          read_enable=1'b0;
          #361  read_enable=1'b1;
          #10  read_enable=1'b0;
          #20 read_enable=1'b1;
          #10  read_enable=1'b0;
          #20 read_enable=1'b1;
          #10  read_enable=1'b0; 
          #20 read_enable=1'b1;
          #10  read_enable=1'b0;
       end  
          
     initial 
       begin                        //testbench
              data=32'h00000000;
          #20 data=32'h2b7e1516;//aes_key=128'h2b7e151628aed2a6abf7158809cf4f3c;
          #20 data=32'h28aed2a6;
          #40 data=32'habf71588;
          #30 data=32'h09cf4f3c;
          #20 data=32'h3243f6a8;//plain_txt=128'h3243f6a8885a308d313198a2e0370734;
          #40 data=32'h885a308d;
          #20 data=32'h313198a2;
          #40 data=32'he0370734;
         
//          #230 data=32'h23571113;//aes_key=128'h2357111317192329abccdefadbeec102;  
//          #10 data=32'h17192329;
//          #10 data=32'habccdefa;
//          #10 data=32'hdbeec102;
//          #10 data=32'h12345678;//plain_txt=128'h1234567890abcdef1234567890abcedf;
//          #10 data=32'h90abcdef;
//          #10 data=32'h12345678;
//          #10 data=32'h90abcedf;
       end
           
     initial 
        begin                        //testbench
               aes_enable=1'b0;
          #241   aes_enable=1'b1;
          #10 aes_enable=1'b0;
//          #290 aes_enable=1'b1;
//          #10   aes_enable=1'b0;

        end
     initial 
        begin                        //testbench
          rst=1'b0;
          #15 rst=1'b1;
          
        end
    initial $monitor($time,,,"data_out=%h", data_out);
    
endmodule