uart_test.v

实现FPGA与PC机的串口通信功能

////////////////////////////////////////////////////////////////////////////
//file name:   Uart_test.v                                                //
//note: write a test file to test uart module                             //
//author: hyw                                                             //
//data: 2007.9.19                                                         //
////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps   //1 ns ---- the time; 100ps----simulation 

module Uart_test();
    //define the regist for the input port
    reg wr;
    reg rst;
    reg clk;
    reg rd;
    reg rxd;
    reg [7:0] data_in;
    reg parity_def;
    
    //define the register for the output port
    wire int;
    wire txd;
    wire dat_rdy;
    wire tbre;
    wire framing_error;
    wire parity_error;
    wire [7:0] data_out;
    
    //define the parameter
    parameter clkvar = 10;

//generate the clk for 50M  
    initial 
       begin                        //testbench
          clk <=1'b1;
       end
    always #clkvar clk <=~clk;

//generate the rst for wait 1.5 us
    initial 
        begin                        //testbench
          rst=1'b0;
          #1500 rst=1'b1;  
        end

//generate the rd=0
initial
   begin
      rd = 1'b0;
   end

//generate the rxd=0
initial
   begin
      rxd = 1'b1;
   end

//generate the data_in = 8'h55; 
initial
   begin
      data_in =  8'h0;
      #1500 data_in = 8'h57;
   end

//generate the wr
initial
   begin
       wr = 1'b0;
       #1500 wr = 1'b1;
       #50 wr = 1'b0;
   end

//generate parity_def = 0
initial
   begin
      parity_def = 1'b0;
   end

//example for uart
 uart   uart_module
    (
    //INPUTS
    .wr            (wr),
    .rst           (rst),
    .clk           (clk),
    .rd            (rd),
    .rxd           (rxd),       
    .data_in       (data_in),
    .parity_def    (parity_def),

    //OUTPUTS
    .int              (int),   
    .txd              (txd),
    .dat_rdy          (dat_rdy),
    .tbre             (tbre),
    .framing_error    (framing_error),
    .parity_error     (parity_error),
    .data_out         (data_out)
    );  
 
endmodule