_primary.vhd

实现FPGA与PC机的串口通信功能

library verilog;
use verilog.vl_types.all;
entity uart_rx is
    port(
        rst             : in     vl_logic;
        clk16x          : in     vl_logic;
        rd              : in     vl_logic;
        rxd             : in     vl_logic;
        parity_def      : in     vl_logic;
        dout            : out    vl_logic_vector(7 downto 0);
        dat_rdy         : out    vl_logic;
        framing_error   : out    vl_logic;
        parity_error    : out    vl_logic
    );
end uart_rx;