vga.map.qmsg

用VHDL写的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 22 13:23:13 2006 " "Info: Processing started: Sat Apr 22 13:23:13 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off VGA -c VGA " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off VGA -c VGA" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "VGA.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file VGA.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 VGA " "Info: Found entity 1: VGA" {  } { { "VGA.bdf" "" { Schematic "F:/qxc/ep2c8/ep2c5/VGA_2c5/VGA.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "VGAsingl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file VGAsingl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 VGAsingl-behav " "Info: Found design unit 1: VGAsingl-behav" {  } { { "VGAsingl.vhd" "" { Text "F:/qxc/ep2c8/ep2c5/VGA_2c5/VGAsingl.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 VGAsingl " "Info: Found entity 1: VGAsingl" {  } { { "VGAsingl.vhd" "" { Text "F:/qxc/ep2c8/ep2c5/VGA_2c5/VGAsingl.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "VGA " "Info: Elaborating entity \"VGA\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGAsingl VGAsingl:inst " "Info: Elaborating entity \"VGAsingl\" for hierarchy \"VGAsingl:inst\"" {  } { { "VGA.bdf" "inst" { Schematic "F:/qxc/ep2c8/ep2c5/VGA_2c5/VGA.bdf" { { 104 296 392 232 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "GRBX VGAsingl.vhd(30) " "Warning (10492): VHDL Process Statement warning at VGAsingl.vhd(30): signal \"GRBX\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "VGAsingl.vhd" "" { Text "F:/qxc/ep2c8/ep2c5/VGA_2c5/VGAsingl.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "GRBY VGAsingl.vhd(31) " "Warning (10492): VHDL Process Statement warning at VGAsingl.vhd(31): signal \"GRBY\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "VGAsingl.vhd" "" { Text "F:/qxc/ep2c8/ep2c5/VGA_2c5/VGAsingl.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "GRBX VGAsingl.vhd(32) " "Warning (10492): VHDL Process Statement warning at VGAsingl.vhd(32): signal \"GRBX\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "VGAsingl.vhd" "" { Text "F:/qxc/ep2c8/ep2c5/VGA_2c5/VGAsingl.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "GRBY VGAsingl.vhd(32) " "Warning (10492): VHDL Process Statement warning at VGAsingl.vhd(32): signal \"GRBY\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "VGAsingl.vhd" "" { Text "F:/qxc/ep2c8/ep2c5/VGA_2c5/VGAsingl.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "70 " "Info: Implemented 70 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "63 " "Info: Implemented 63 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 22 13:23:21 2006 " "Info: Processing ended: Sat Apr 22 13:23:21 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}