dds.map.eqn

这是一个用vhdl语言实现dds的例子

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--E1_q_a[7] is rom01:inst1|altsyncram:altsyncram_component|altsyncram_ipr:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
E1_q_a[7]_PORT_A_address = BUS(B1_adda[0], B1_adda[1], B1_adda[2], B1_adda[3], B1_adda[4], B1_adda[5], B1_adda[6], B1_adda[7]);
E1_q_a[7]_PORT_A_address_reg = DFFE(E1_q_a[7]_PORT_A_address, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_clock_0 = !clk;
E1_q_a[7]_PORT_A_data_out = MEMORY(, , E1_q_a[7]_PORT_A_address_reg, , , , , , E1_q_a[7]_clock_0, , , , , );
E1_q_a[7]_PORT_A_data_out_reg = DFFE(E1_q_a[7]_PORT_A_data_out, E1_q_a[7]_clock_0, , , );
E1_q_a[7] = E1_q_a[7]_PORT_A_data_out_reg[0];


--E1_q_a[6] is rom01:inst1|altsyncram:altsyncram_component|altsyncram_ipr:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
E1_q_a[6]_PORT_A_address = BUS(B1_adda[0], B1_adda[1], B1_adda[2], B1_adda[3], B1_adda[4], B1_adda[5], B1_adda[6], B1_adda[7]);
E1_q_a[6]_PORT_A_address_reg = DFFE(E1_q_a[6]_PORT_A_address, E1_q_a[6]_clock_0, , , );
E1_q_a[6]_clock_0 = !clk;
E1_q_a[6]_PORT_A_data_out = MEMORY(, , E1_q_a[6]_PORT_A_address_reg, , , , , , E1_q_a[6]_clock_0, , , , , );
E1_q_a[6]_PORT_A_data_out_reg = DFFE(E1_q_a[6]_PORT_A_data_out, E1_q_a[6]_clock_0, , , );
E1_q_a[6] = E1_q_a[6]_PORT_A_data_out_reg[0];


--E1_q_a[5] is rom01:inst1|altsyncram:altsyncram_component|altsyncram_ipr:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
E1_q_a[5]_PORT_A_address = BUS(B1_adda[0], B1_adda[1], B1_adda[2], B1_adda[3], B1_adda[4], B1_adda[5], B1_adda[6], B1_adda[7]);
E1_q_a[5]_PORT_A_address_reg = DFFE(E1_q_a[5]_PORT_A_address, E1_q_a[5]_clock_0, , , );
E1_q_a[5]_clock_0 = !clk;
E1_q_a[5]_PORT_A_data_out = MEMORY(, , E1_q_a[5]_PORT_A_address_reg, , , , , , E1_q_a[5]_clock_0, , , , , );
E1_q_a[5]_PORT_A_data_out_reg = DFFE(E1_q_a[5]_PORT_A_data_out, E1_q_a[5]_clock_0, , , );
E1_q_a[5] = E1_q_a[5]_PORT_A_data_out_reg[0];


--E1_q_a[4] is rom01:inst1|altsyncram:altsyncram_component|altsyncram_ipr:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
E1_q_a[4]_PORT_A_address = BUS(B1_adda[0], B1_adda[1], B1_adda[2], B1_adda[3], B1_adda[4], B1_adda[5], B1_adda[6], B1_adda[7]);
E1_q_a[4]_PORT_A_address_reg = DFFE(E1_q_a[4]_PORT_A_address, E1_q_a[4]_clock_0, , , );
E1_q_a[4]_clock_0 = !clk;
E1_q_a[4]_PORT_A_data_out = MEMORY(, , E1_q_a[4]_PORT_A_address_reg, , , , , , E1_q_a[4]_clock_0, , , , , );
E1_q_a[4]_PORT_A_data_out_reg = DFFE(E1_q_a[4]_PORT_A_data_out, E1_q_a[4]_clock_0, , , );
E1_q_a[4] = E1_q_a[4]_PORT_A_data_out_reg[0];


--E1_q_a[3] is rom01:inst1|altsyncram:altsyncram_component|altsyncram_ipr:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
E1_q_a[3]_PORT_A_address = BUS(B1_adda[0], B1_adda[1], B1_adda[2], B1_adda[3], B1_adda[4], B1_adda[5], B1_adda[6], B1_adda[7]);
E1_q_a[3]_PORT_A_address_reg = DFFE(E1_q_a[3]_PORT_A_address, E1_q_a[3]_clock_0, , , );
E1_q_a[3]_clock_0 = !clk;
E1_q_a[3]_PORT_A_data_out = MEMORY(, , E1_q_a[3]_PORT_A_address_reg, , , , , , E1_q_a[3]_clock_0, , , , , );
E1_q_a[3]_PORT_A_data_out_reg = DFFE(E1_q_a[3]_PORT_A_data_out, E1_q_a[3]_clock_0, , , );
E1_q_a[3] = E1_q_a[3]_PORT_A_data_out_reg[0];


--E1_q_a[2] is rom01:inst1|altsyncram:altsyncram_component|altsyncram_ipr:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
E1_q_a[2]_PORT_A_address = BUS(B1_adda[0], B1_adda[1], B1_adda[2], B1_adda[3], B1_adda[4], B1_adda[5], B1_adda[6], B1_adda[7]);
E1_q_a[2]_PORT_A_address_reg = DFFE(E1_q_a[2]_PORT_A_address, E1_q_a[2]_clock_0, , , );
E1_q_a[2]_clock_0 = !clk;
E1_q_a[2]_PORT_A_data_out = MEMORY(, , E1_q_a[2]_PORT_A_address_reg, , , , , , E1_q_a[2]_clock_0, , , , , );
E1_q_a[2]_PORT_A_data_out_reg = DFFE(E1_q_a[2]_PORT_A_data_out, E1_q_a[2]_clock_0, , , );
E1_q_a[2] = E1_q_a[2]_PORT_A_data_out_reg[0];


--E1_q_a[1] is rom01:inst1|altsyncram:altsyncram_component|altsyncram_ipr:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
E1_q_a[1]_PORT_A_address = BUS(B1_adda[0], B1_adda[1], B1_adda[2], B1_adda[3], B1_adda[4], B1_adda[5], B1_adda[6], B1_adda[7]);
E1_q_a[1]_PORT_A_address_reg = DFFE(E1_q_a[1]_PORT_A_address, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_clock_0 = !clk;
E1_q_a[1]_PORT_A_data_out = MEMORY(, , E1_q_a[1]_PORT_A_address_reg, , , , , , E1_q_a[1]_clock_0, , , , , );
E1_q_a[1]_PORT_A_data_out_reg = DFFE(E1_q_a[1]_PORT_A_data_out, E1_q_a[1]_clock_0, , , );
E1_q_a[1] = E1_q_a[1]_PORT_A_data_out_reg[0];


--E1_q_a[0] is rom01:inst1|altsyncram:altsyncram_component|altsyncram_ipr:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
E1_q_a[0]_PORT_A_address = BUS(B1_adda[0], B1_adda[1], B1_adda[2], B1_adda[3], B1_adda[4], B1_adda[5], B1_adda[6], B1_adda[7]);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_clock_0 = !clk;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , , , , );
E1_q_a[0]_PORT_A_data_out_reg = DFFE(E1_q_a[0]_PORT_A_data_out, E1_q_a[0]_clock_0, , , );
E1_q_a[0] = E1_q_a[0]_PORT_A_data_out_reg[0];


--B1_adda[0] is add:inst|adda[0]
--operation mode is normal

B1_adda[0]_lut_out = B1_back[8];
B1_adda[0] = DFFEAS(B1_adda[0]_lut_out, clk, VCC, , , , , , );


--B1_adda[1] is add:inst|adda[1]
--operation mode is normal

B1_adda[1]_lut_out = B1_back[9];
B1_adda[1] = DFFEAS(B1_adda[1]_lut_out, clk, VCC, , , , , , );


--B1_adda[2] is add:inst|adda[2]
--operation mode is normal

B1_adda[2]_lut_out = B1_back[10];
B1_adda[2] = DFFEAS(B1_adda[2]_lut_out, clk, VCC, , , , , , );


--B1_adda[3] is add:inst|adda[3]
--operation mode is normal

B1_adda[3]_lut_out = B1_back[11];
B1_adda[3] = DFFEAS(B1_adda[3]_lut_out, clk, VCC, , , , , , );


--B1_adda[4] is add:inst|adda[4]
--operation mode is normal

B1_adda[4]_lut_out = B1_back[12];
B1_adda[4] = DFFEAS(B1_adda[4]_lut_out, clk, VCC, , , , , , );


--B1_adda[5] is add:inst|adda[5]
--operation mode is normal

B1_adda[5]_lut_out = B1_back[13];
B1_adda[5] = DFFEAS(B1_adda[5]_lut_out, clk, VCC, , , , , , );


--B1_adda[6] is add:inst|adda[6]
--operation mode is normal

B1_adda[6]_lut_out = B1_back[14];
B1_adda[6] = DFFEAS(B1_adda[6]_lut_out, clk, VCC, , , , , , );


--B1_adda[7] is add:inst|adda[7]
--operation mode is normal

B1_adda[7]_lut_out = B1_back[15];
B1_adda[7] = DFFEAS(B1_adda[7]_lut_out, clk, VCC, , , , , , );


--B1_back[8] is add:inst|back[8]
--operation mode is arithmetic

B1_back[8]_carry_eqn = B1L26;
B1_back[8]_lut_out = B1_back[8] $ (!B1_back[8]_carry_eqn);
B1_back[8] = DFFEAS(B1_back[8]_lut_out, clk, VCC, , , , , , );

--B1L28 is add:inst|back[8]~113
--operation mode is arithmetic

B1L28 = CARRY(B1_back[8] & (!B1L26));


--B1_back[9] is add:inst|back[9]
--operation mode is arithmetic

B1_back[9]_carry_eqn = B1L28;
B1_back[9]_lut_out = B1_back[9] $ (B1_back[9]_carry_eqn);
B1_back[9] = DFFEAS(B1_back[9]_lut_out, clk, VCC, , , , , , );

--B1L30 is add:inst|back[9]~117
--operation mode is arithmetic

B1L30 = CARRY(!B1L28 # !B1_back[9]);


--B1_back[10] is add:inst|back[10]
--operation mode is arithmetic

B1_back[10]_carry_eqn = B1L30;
B1_back[10]_lut_out = B1_back[10] $ (!B1_back[10]_carry_eqn);
B1_back[10] = DFFEAS(B1_back[10]_lut_out, clk, VCC, , , , , , );

--B1L32 is add:inst|back[10]~121
--operation mode is arithmetic

B1L32 = CARRY(B1_back[10] & (!B1L30));


--B1_back[11] is add:inst|back[11]
--operation mode is arithmetic

B1_back[11]_carry_eqn = B1L32;
B1_back[11]_lut_out = B1_back[11] $ (B1_back[11]_carry_eqn);
B1_back[11] = DFFEAS(B1_back[11]_lut_out, clk, VCC, , , , , , );

--B1L34 is add:inst|back[11]~125
--operation mode is arithmetic

B1L34 = CARRY(!B1L32 # !B1_back[11]);


--B1_back[12] is add:inst|back[12]
--operation mode is arithmetic

B1_back[12]_carry_eqn = B1L34;
B1_back[12]_lut_out = B1_back[12] $ (!B1_back[12]_carry_eqn);
B1_back[12] = DFFEAS(B1_back[12]_lut_out, clk, VCC, , , , , , );

--B1L36 is add:inst|back[12]~129
--operation mode is arithmetic

B1L36 = CARRY(B1_back[12] & (!B1L34));


--B1_back[13] is add:inst|back[13]
--operation mode is arithmetic

B1_back[13]_carry_eqn = B1L36;
B1_back[13]_lut_out = B1_back[13] $ (B1_back[13]_carry_eqn);
B1_back[13] = DFFEAS(B1_back[13]_lut_out, clk, VCC, , , , , , );

--B1L38 is add:inst|back[13]~133
--operation mode is arithmetic

B1L38 = CARRY(!B1L36 # !B1_back[13]);


--B1_back[14] is add:inst|back[14]
--operation mode is arithmetic

B1_back[14]_carry_eqn = B1L38;
B1_back[14]_lut_out = B1_back[14] $ (!B1_back[14]_carry_eqn);
B1_back[14] = DFFEAS(B1_back[14]_lut_out, clk, VCC, , , , , , );

--B1L40 is add:inst|back[14]~137
--operation mode is arithmetic

B1L40 = CARRY(B1_back[14] & (!B1L38));


--B1_back[15] is add:inst|back[15]
--operation mode is normal

B1_back[15]_carry_eqn = B1L40;
B1_back[15]_lut_out = B1_back[15] $ (B1_back[15]_carry_eqn);
B1_back[15] = DFFEAS(B1_back[15]_lut_out, clk, VCC, , , , , , );


--B1_back[7] is add:inst|back[7]
--operation mode is arithmetic

B1_back[7]_carry_eqn = B1L24;
B1_back[7]_lut_out = B1_back[7] $ m[7] $ B1_back[7]_carry_eqn;
B1_back[7] = DFFEAS(B1_back[7]_lut_out, clk, VCC, , , , , , );

--B1L26 is add:inst|back[7]~145
--operation mode is arithmetic

B1L26 = CARRY(B1_back[7] & !m[7] & !B1L24 # !B1_back[7] & (!B1L24 # !m[7]));


--B1_back[6] is add:inst|back[6]
--operation mode is arithmetic

B1_back[6]_carry_eqn = B1L22;
B1_back[6]_lut_out = B1_back[6] $ m[6] $ !B1_back[6]_carry_eqn;
B1_back[6] = DFFEAS(B1_back[6]_lut_out, clk, VCC, , , , , , );

--B1L24 is add:inst|back[6]~149
--operation mode is arithmetic

B1L24 = CARRY(B1_back[6] & (m[6] # !B1L22) # !B1_back[6] & m[6] & !B1L22);


--B1_back[5] is add:inst|back[5]
--operation mode is arithmetic

B1_back[5]_carry_eqn = B1L20;
B1_back[5]_lut_out = B1_back[5] $ m[5] $ B1_back[5]_carry_eqn;
B1_back[5] = DFFEAS(B1_back[5]_lut_out, clk, VCC, , , , , , );

--B1L22 is add:inst|back[5]~153
--operation mode is arithmetic

B1L22 = CARRY(B1_back[5] & !m[5] & !B1L20 # !B1_back[5] & (!B1L20 # !m[5]));


--B1_back[4] is add:inst|back[4]
--operation mode is arithmetic

B1_back[4]_carry_eqn = B1L18;
B1_back[4]_lut_out = B1_back[4] $ m[4] $ !B1_back[4]_carry_eqn;
B1_back[4] = DFFEAS(B1_back[4]_lut_out, clk, VCC, , , , , , );

--B1L20 is add:inst|back[4]~157
--operation mode is arithmetic

B1L20 = CARRY(B1_back[4] & (m[4] # !B1L18) # !B1_back[4] & m[4] & !B1L18);


--B1_back[3] is add:inst|back[3]
--operation mode is arithmetic

B1_back[3]_carry_eqn = B1L16;
B1_back[3]_lut_out = B1_back[3] $ m[3] $ B1_back[3]_carry_eqn;
B1_back[3] = DFFEAS(B1_back[3]_lut_out, clk, VCC, , , , , , );

--B1L18 is add:inst|back[3]~161
--operation mode is arithmetic

B1L18 = CARRY(B1_back[3] & !m[3] & !B1L16 # !B1_back[3] & (!B1L16 # !m[3]));


--B1_back[2] is add:inst|back[2]
--operation mode is arithmetic

B1_back[2]_carry_eqn = B1L14;
B1_back[2]_lut_out = B1_back[2] $ m[2] $ !B1_back[2]_carry_eqn;
B1_back[2] = DFFEAS(B1_back[2]_lut_out, clk, VCC, , , , , , );

--B1L16 is add:inst|back[2]~165
--operation mode is arithmetic

B1L16 = CARRY(B1_back[2] & (m[2] # !B1L14) # !B1_back[2] & m[2] & !B1L14);


--B1_back[1] is add:inst|back[1]
--operation mode is arithmetic

B1_back[1]_carry_eqn = B1L12;
B1_back[1]_lut_out = B1_back[1] $ m[1] $ B1_back[1]_carry_eqn;
B1_back[1] = DFFEAS(B1_back[1]_lut_out, clk, VCC, , , , , , );

--B1L14 is add:inst|back[1]~169
--operation mode is arithmetic

B1L14 = CARRY(B1_back[1] & !m[1] & !B1L12 # !B1_back[1] & (!B1L12 # !m[1]));


--B1_back[0] is add:inst|back[0]
--operation mode is arithmetic

B1_back[0]_lut_out = B1_back[0] $ m[0];
B1_back[0] = DFFEAS(B1_back[0]_lut_out, clk, VCC, , , , , , );

--B1L12 is add:inst|back[0]~173
--operation mode is arithmetic

B1L12 = CARRY(B1_back[0] & m[0]);


--clk is clk
--operation mode is input

clk = INPUT();


--m[7] is m[7]
--operation mode is input

m[7] = INPUT();


--m[6] is m[6]
--operation mode is input

m[6] = INPUT();


--m[5] is m[5]
--operation mode is input

m[5] = INPUT();


--m[4] is m[4]
--operation mode is input

m[4] = INPUT();


--m[3] is m[3]
--operation mode is input

m[3] = INPUT();


--m[2] is m[2]
--operation mode is input

m[2] = INPUT();


--m[1] is m[1]
--operation mode is input

m[1] = INPUT();


--m[0] is m[0]
--operation mode is input

m[0] = INPUT();


--out[7] is out[7]
--operation mode is output

out[7] = OUTPUT(E1_q_a[7]);


--out[6] is out[6]
--operation mode is output

out[6] = OUTPUT(E1_q_a[6]);


--out[5] is out[5]
--operation mode is output

out[5] = OUTPUT(E1_q_a[5]);


--out[4] is out[4]
--operation mode is output

out[4] = OUTPUT(E1_q_a[4]);


--out[3] is out[3]
--operation mode is output

out[3] = OUTPUT(E1_q_a[3]);


--out[2] is out[2]
--operation mode is output

out[2] = OUTPUT(E1_q_a[2]);


--out[1] is out[1]
--operation mode is output

out[1] = OUTPUT(E1_q_a[1]);


--out[0] is out[0]
--operation mode is output

out[0] = OUTPUT(E1_q_a[0]);