dds.tan.rpt

来自「这是一个用vhdl语言实现dds的例子」· RPT 代码 · 共 221 行 · 第 1/5 页

; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg3 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg4 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg5 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg6 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg7 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg1 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg2 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg3 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg4 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg5 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg6 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg7 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg1 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg2 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg3 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg4 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg5 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg6 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg7 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[8]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg1 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[8]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg2 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[8]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg3 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[8]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg4 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[8]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg5 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[8]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg6 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[8]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg7 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[8]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[9]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg1 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[9]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg2 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[9]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg3 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[9]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg4 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[9]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg5 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[9]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg6 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[9]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg7 ; rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[9]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; 311.43 MHz ( period = 3.211 ns )                    ; add:inst|back[0]                                                                                           ; add:inst|back[15]                                                                                          ; clk        ; clk      ; None                        ; None                      ; 2.947 ns                ;
; N/A                                     ; 319.08 MHz ( period = 3.134 ns )                    ; add:inst|back[1]                                                                                           ; add:inst|back[15]                                                                                          ; clk        ; clk      ; None                        ; None                      ; 2.870 ns                ;
; N/A                                     ; 320.00 MHz ( period = 3.125 ns )                    ; add:inst|back[0]                                                                                           ; add:inst|back[14]                                                                                          ; clk        ; clk      ; None                        ; None                      ; 2.861 ns                ;
; N/A                                     ; 327.98 MHz ( period = 3.049 ns )                    ; add:inst|back[2]                                                                                           ; add:inst|back[15]                                                                                          ; clk        ; clk      ; None                        ; None                      ; 2.785 ns                ;
; N/A                                     ; 328.08 MHz ( period = 3.048 ns )                    ; add:inst|back[1]                                                                                           ; add:inst|back[14]                                                                                          ; clk        ; clk      ; None                        ; None                      ; 2.784 ns                ;
; N/A                                     ; 329.06 MHz ( period = 3.039 ns )                    ; add:inst|back[0]                                                                                           ; add:inst|back[13]                                                                                          ; clk        ; clk      ; None                        ; None                      ; 2.775 ns                ;
; N/A                                     ; 331.90 MHz ( period = 3.013 ns )                    ; add:inst|back[3]                                                                                           ; add:inst|back[15]                                                                                          ; clk        ; clk      ; None                        ; None                      ; 2.749 ns                ;
; N/A                                     ; 337.50 MHz ( period = 2.963 ns )                    ; add:inst|back[2]                                                                                           ; add:inst|back[14]                                                                                          ; clk        ; clk      ; None                        ; None                      ; 2.699 ns                ;