counter.vhd

来自「异步串口通信VHDL源代码」· VHDL 代码 · 共 29 行

-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
-- 实体声明
entity counter is
	generic (
	MAX_COUNT : integer := 10 );
	port (
	clk : in std_logic;
	reset_n : in std_logic;
	ce : in std_logic;
	overflow : out std_logic;
	
	dout : out std_logic_vector(3 downto 0)
	);
end counter;

--}} End of automatically maintained section
-- 结构体
architecture counter of counter is

signal count : integer;

begin

	dout <= conv_std_logic_vector(count, 4);
	-- enter your statements here --
	-- 主