uart_top.vhd

异步串口通信VHDL源代码

library IEEE;
use IEEE.std_logic_1164.all;
use WORK.UART_PACKAGE.all;

entity uart_top is

  generic(
     -- 数据位个数
	DATA_BIT : integer := 8;
	-- 总数据个数
	TOTAL_BIT : integer := 11;		--liujl
	-- 奇偶校验规则
	PARITY_RULE : PARITY := EVEN;
	--完整波特率时钟对应的计数
	FULL_PULSE_COUNT : BD_COUNT := 1302;--BDTEST_FPC;
	--波特率时钟上升沿对应的计数
	RISE_PULSE_COUNT : BD_COUNT := 651--BDTEST_HPC 
  );
  port(
	  -- 时钟信号
     --  clk : in STD_LOGIC;		
		 clk : in STD_LOGIC;	
	  -- 复位信号
       reset_n : in STD_LOGIC;
	  -- 发送控制信号
       send : in STD_LOGIC;
	  -- 数据发送总线
       send_bus : in STD_LOGIC_VECTOR(DATA_BIT-1 downto 0);
	  -- 发送完成信号
       send_over : out STD_LOGIC;
	  -- 错误提示信号
       error : out STD_LOGIC;
	  -- 接收提示信号
       recv : out STD_LOGIC;
	  -- 数据接收总线
       recv_bus : out STD_LOGIC_VECTOR(DATA_BIT-1 downto 0);
	  -- RS-232数据接收端口
       RxD : in STD_LOGIC;
	  -- RS-232数据发送端口
       TxD : out STD_LOGIC
		 );
end uart_top;

architecture uart_top of uart_top is

-- 波特率发生器组件声明
component baudrate_generator
  generic(
       FULL_PULSE_COUNT : BD_COUNT := FULL_PULSE_COUNT;		--liujl
       RISE_PULSE_COUNT : BD_COUNT := RISE_PULSE_COUNT		--liujl
  );
  port (
       ce : in STD_LOGIC;
       clk : in STD_LOGIC;
       reset_n : in STD_LOGIC;
       bg_out : out STD_LOGIC;
       indicator : out STD_LOGIC
  );
end component;
-- 计数器组件声明
component counter
  generic(
       MAX_COUNT : INTEGER := TOTAL_BIT		--liujl
  );
  port (
       ce : in STD_LOGIC;
       clk : in STD_LOGIC;
       reset_n : in STD_LOGIC;
       overflow : out STD_LOGIC;
		 
		 dout : inout std_logic_vector(3 downto 0)
  );
end component;
-- 信号监测?
component detector
  port (
       RxD : in STD_LOGIC;
       clk : in STD_LOGIC;
       reset_n : in STD_LOGIC;
       new_data : out STD_LOGIC
  );
end component;
-- 奇偶校验器
component parity_verifier
  generic(
       DATA_LENGTH : INTEGER := DATA_BIT;
       PARITY_RULE : PARITY := PARITY_RULE
  );
  port (
       source : in STD_LOGIC_VECTOR(DATA_LENGTH-1 downto 0);
       parity : out STD_LOGIC
  );
end component;
-- 移位寄存器
component shift_register
  generic(
       TOTAL_BIT : INTEGER := TOTAL_BIT
  );
  port (
       clk : in STD_LOGIC;
       din : in STD_LOGIC;
       reset_n : in STD_LOGIC;
       dout : out STD_LOGIC;
       regs : out STD_LOGIC_VECTOR(TOTAL_BIT-1 downto 0)
  );
end component;
-- 二选一选择器
component switch
  port (
       din1 : in STD_LOGIC;
       din2 : in STD_LOGIC;
       sel : in STD_LOGIC;
       dout : out STD_LOGIC
  );
end component;
-- 总线选择器
component switch_bus
  generic(
       BUS_WIDTH : INTEGER := DATA_BIT
  );
  port (
       din1 : in STD_LOGIC_VECTOR(BUS_WIDTH-1 downto 0);
       din2 : in STD_LOGIC_VECTOR(BUS_WIDTH-1 downto 0);
       sel : in STD_LOGIC;
       dout : out STD_LOGIC_VECTOR(BUS_WIDTH-1 downto 0)
  );
end component;
-- UART内核
component uart_core
  generic(
       DATA_BIT : INTEGER := DATA_BIT;
       PARITY_RULE : PARITY := PARITY_RULE;
       TOTAL_BIT : INTEGER := TOTAL_BIT
  );
  port (
       clk : in STD_LOGIC;
       new_data : in STD_LOGIC;
       overflow : in STD_LOGIC;
       parity : in STD_LOGIC;
       regs : in STD_LOGIC_VECTOR(TOTAL_BIT-1 downto 0);
       reset_n : in STD_LOGIC;
       send : in STD_LOGIC;
       send_bus : in STD_LOGIC_VECTOR(DATA_BIT-1 downto 0);
       ce_parts : out STD_LOGIC;
       error : out STD_LOGIC;
       recv : out STD_LOGIC;
       recv_bus : out STD_LOGIC_VECTOR(DATA_BIT-1 downto 0);
       reset_dt : out STD_LOGIC;
       reset_parts : out STD_LOGIC;
       sel_clk : out STD_LOGIC;
       sel_out : out STD_LOGIC;
       sel_pv : out STD_LOGIC;
       sel_si : out STD_LOGIC;
       send_over : out STD_LOGIC;
       send_si : out STD_LOGIC;
		 
		 send_buf : inout std_logic_vector(TOTAL_BIT-1 downto 0)
  );
end component;


----     常数     -----
constant VCC_CONSTANT   : STD_LOGIC := '1';
---- 内部信号声明 ----
signal bg_clk : STD_LOGIC;
signal bg_out : STD_LOGIC;
signal ce_parts : STD_LOGIC;
signal clk_inv : STD_LOGIC;
signal counter_clk : STD_LOGIC;
signal indicator : STD_LOGIC;
signal new_data : STD_LOGIC;
signal overflow : STD_LOGIC;
signal parity : STD_LOGIC;
signal reset_dt : STD_LOGIC;
signal reset_parts : STD_LOGIC;
signal sel_clk : STD_LOGIC;
signal sel_out : STD_LOGIC;
signal sel_pv : STD_LOGIC;
signal sel_si : STD_LOGIC;
signal send_si : STD_LOGIC;
signal sr_in : STD_LOGIC;
signal sr_out : STD_LOGIC;
signal VCC : STD_LOGIC;
signal pv_source : STD_LOGIC_VECTOR (DATA_BIT-1 downto 0);
signal recv_parity_source : STD_LOGIC_VECTOR (DATA_BIT-1 downto 0);
signal regs : STD_LOGIC_VECTOR (TOTAL_BIT-1 downto 0);
signal send_parity_source : STD_LOGIC_VECTOR (DATA_BIT-1 downto 0);

begin

	clk_inv <= not clk;
	VCC <= VCC_CONSTANT;   
	send_parity_source <= send_bus;
	recv_bus <= recv_parity_source;
	
	-- 波芈盛生?	
	U_BG : baudrate_generator
	  port map(
	       bg_out => bg_out,
	       ce => ce_parts,
	       clk => clk,
	       indicator => indicator,
	       reset_n => reset_parts
	  );
	-- 总线选择器实例
	U_BusSwitch : switch_bus
	  port map(
	       din1 => send_parity_source( DATA_BIT-1 downto 0 ),
	       din2 => recv_parity_source( DATA_BIT-1 downto 0 ),
	       dout => pv_source( DATA_BIT-1 downto 0 ),
	       sel => sel_pv
	  );
	-- UART内核道?	
	U_Core : uart_core
	  port map(
	       ce_parts => ce_parts,
	       clk => clk,
	       error => error,
	       new_data => new_data,
	       overflow => overflow,
	       parity => parity,
	       recv => recv,
	       recv_bus => recv_parity_source( DATA_BIT-1 downto 0 ),
	       regs => regs( TOTAL_BIT-1 downto 0 ),
	       reset_dt => reset_dt,
	       reset_n => reset_n,
	       reset_parts => reset_parts,
	       sel_clk => sel_clk,
	       sel_out => sel_out,
	       sel_pv => sel_pv,
	       sel_si => sel_si,
	       send => send,
	       send_bus => send_parity_source( DATA_BIT-1 downto 0 ),
	       send_over => send_over,
	       send_si => send_si
			 
	  );
	-- 计数器实例
	U_Counter : counter
	  port map(
	       ce => ce_parts,
	       clk => counter_clk,
	       overflow => overflow,
	       reset_n => reset_parts
	  );
	
	-- 计数魇敝釉囱择器
	U_CounterClkSwitch : switch
	  port map(
	       din1 => indicator,
	       din2 => clk_inv,
	       dout => counter_clk,
	       sel => sel_clk
	  );
	-- 信号监馄?	
	U_Detector : detector
	  port map(
	       RxD => RxD,
	       clk => clk,
	       new_data => new_data,
	       reset_n => reset_dt
	  );
	-- 奇夹Ｑ槠?	
	U_ParityVerifier : parity_verifier
	  port map(
	       parity => parity,
	       source => pv_source( DATA_BIT-1 downto 0 )
	  );
	-- 移位寄存器输入源选衿魇道?
	U_SISwitch : switch
	  port map(
	       din1 => send_si,
	       din2 => RxD,
	       dout => sr_in,
	       sel => sel_si
	  );
	-- 移位寄存器实例
	U_SR : shift_register
	  port map(
	       clk => bg_clk,
	       din => sr_in,
	       dout => sr_out,
	       regs => regs( TOTAL_BIT-1 downto 0 ),
	       reset_n => reset_parts
	  );
	-- 苹寄存器时钟源选衿魇?	
	U_SRClkSwitch : switch
	  port map(
	       din1 => bg_out,
	       din2 => clk_inv,
	       dout => bg_clk,
	       sel => sel_clk
	  );
	-- 输出选择器实例
	U_TXDSwitch : switch
	  port map(
	       din1 => VCC,
	       din2 => sr_out,
	       dout => TxD,
	       sel => sel_out
	  );

end uart_top;