dpram.vhd

异步串口通信VHDL源代码

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:09:14 01/04/2008 
-- Design Name: 
-- Module Name:    dpRam - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DRam_256_8 is
    Port ( clk : in  STD_LOGIC;
           wr_en : in  STD_LOGIC;
           rd_en : in  STD_LOGIC;
           din : in  STD_LOGIC_VECTOR (7 downto 0);
           dout : out  STD_LOGIC_VECTOR (7 downto 0);
           addr : in  STD_LOGIC_VECTOR (7 downto 0) := (others => '0')
			);
end DRam_256_8;

architecture Behavioral of DRam_256_8 is
	subtype ram_word is std_logic_vector(7 downto 0);
	type ram_table is array (0 to 255) of ram_word;
	signal ram: ram_table; 
	
	signal addr_buf: integer range 0 to 255 ;
begin

	addr_buf <= CONV_INTEGER(addr);
	
	pread: process(clk)
	begin
		if rising_edge(clk) then
			if rd_en = '1' then
				dout <= ram(addr_buf);
			else
				dout <= (others => 'X');
			end if;
		end if;
	end process;
	
	pwrite: process(clk)
	begin
		if rising_edge(clk) then
			if wr_en = '1' then
				ram(addr_buf) <= din;
			end if;
		end if;
	end process;

end Behavioral;