vrms_ram_ctrl.hier_info

使用VHDL语言描述AD0809芯片功能

denominator[2] => alt_u_div_mve:divider.denominator[2]
denominator[2] => op_1.IN3
denominator[3] => alt_u_div_mve:divider.denominator[3]
denominator[3] => op_1.IN1
numerator[0] => alt_u_div_mve:divider.numerator[0]
numerator[1] => alt_u_div_mve:divider.numerator[1]
numerator[2] => alt_u_div_mve:divider.numerator[2]
numerator[3] => alt_u_div_mve:divider.numerator[3]
numerator[4] => alt_u_div_mve:divider.numerator[4]
numerator[5] => alt_u_div_mve:divider.numerator[5]
numerator[6] => alt_u_div_mve:divider.numerator[6]
quotient[0] <= protect_quotient[0].DB_MAX_OUTPUT_PORT_TYPE
quotient[1] <= protect_quotient[1].DB_MAX_OUTPUT_PORT_TYPE
quotient[2] <= protect_quotient[2].DB_MAX_OUTPUT_PORT_TYPE
quotient[3] <= protect_quotient[3].DB_MAX_OUTPUT_PORT_TYPE
quotient[4] <= protect_quotient[4].DB_MAX_OUTPUT_PORT_TYPE
quotient[5] <= protect_quotient[5].DB_MAX_OUTPUT_PORT_TYPE
quotient[6] <= protect_quotient[6].DB_MAX_OUTPUT_PORT_TYPE
remainder[0] <= protect_remainder[0].DB_MAX_OUTPUT_PORT_TYPE
remainder[1] <= protect_remainder[1].DB_MAX_OUTPUT_PORT_TYPE
remainder[2] <= protect_remainder[2].DB_MAX_OUTPUT_PORT_TYPE
remainder[3] <= protect_remainder[3].DB_MAX_OUTPUT_PORT_TYPE


|Vrms_ram_ctrl|divide10_99:divide10_99a|lpm_divide:lpm_divide_component|lpm_divide_frp:auto_generated|sign_div_unsign_akh:divider|alt_u_div_mve:divider
den_out[0] <= DenominatorIn[30].DB_MAX_OUTPUT_PORT_TYPE
den_out[1] <= DenominatorIn[31].DB_MAX_OUTPUT_PORT_TYPE
den_out[2] <= DenominatorIn[32].DB_MAX_OUTPUT_PORT_TYPE
den_out[3] <= DenominatorIn[33].DB_MAX_OUTPUT_PORT_TYPE
denominator[0] => DenominatorIn[0].IN1
denominator[1] => DenominatorIn[1].IN1
denominator[2] => DenominatorIn[2].IN1
denominator[3] => DenominatorIn[3].IN1
numerator[0] => NumeratorIn[0].IN1
numerator[1] => NumeratorIn[1].IN1
numerator[2] => NumeratorIn[2].IN1
numerator[3] => NumeratorIn[3].IN1
numerator[4] => NumeratorIn[4].IN1
numerator[5] => NumeratorIn[5].IN1
numerator[6] => NumeratorIn[6].IN1
quotient[0] <= quotient_tmp[0].DB_MAX_OUTPUT_PORT_TYPE
quotient[1] <= quotient_tmp[1].DB_MAX_OUTPUT_PORT_TYPE
quotient[2] <= quotient_tmp[2].DB_MAX_OUTPUT_PORT_TYPE
quotient[3] <= quotient_tmp[3].DB_MAX_OUTPUT_PORT_TYPE
quotient[4] <= quotient_tmp[4].DB_MAX_OUTPUT_PORT_TYPE
quotient[5] <= quotient_tmp[5].DB_MAX_OUTPUT_PORT_TYPE
quotient[6] <= quotient_tmp[6].DB_MAX_OUTPUT_PORT_TYPE
remainder[0] <= StageIn[35].DB_MAX_OUTPUT_PORT_TYPE
remainder[1] <= StageIn[36].DB_MAX_OUTPUT_PORT_TYPE
remainder[2] <= StageIn[37].DB_MAX_OUTPUT_PORT_TYPE
remainder[3] <= StageIn[38].DB_MAX_OUTPUT_PORT_TYPE


|Vrms_ram_ctrl|divide10_99:divide10_99a|lpm_divide:lpm_divide_component|lpm_divide_frp:auto_generated|sign_div_unsign_akh:divider|alt_u_div_mve:divider|add_sub_lkc:add_sub_0
cout <= carry_eqn[0].DB_MAX_OUTPUT_PORT_TYPE
datab[0] => datab_node[0].IN0
result[0] <= sum_eqn[0].DB_MAX_OUTPUT_PORT_TYPE


|Vrms_ram_ctrl|divide10_99:divide10_99a|lpm_divide:lpm_divide_component|lpm_divide_frp:auto_generated|sign_div_unsign_akh:divider|alt_u_div_mve:divider|add_sub_mkc:add_sub_1
cout <= carry_eqn[1].DB_MAX_OUTPUT_PORT_TYPE
datab[0] => datab_node[0].IN0
datab[1] => datab_node[1].IN0
result[0] <= sum_eqn[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= sum_eqn[1].DB_MAX_OUTPUT_PORT_TYPE


|Vrms_ram_ctrl|Vrms_ram:Vrms_ram1
data[0] => altsyncram:altsyncram_component.data_a[0]
data[1] => altsyncram:altsyncram_component.data_a[1]
data[2] => altsyncram:altsyncram_component.data_a[2]
data[3] => altsyncram:altsyncram_component.data_a[3]
data[4] => altsyncram:altsyncram_component.data_a[4]
data[5] => altsyncram:altsyncram_component.data_a[5]
data[6] => altsyncram:altsyncram_component.data_a[6]
data[7] => altsyncram:altsyncram_component.data_a[7]
rdaddress[0] => altsyncram:altsyncram_component.address_b[0]
rdaddress[1] => altsyncram:altsyncram_component.address_b[1]
rdaddress[2] => altsyncram:altsyncram_component.address_b[2]
rdaddress[3] => altsyncram:altsyncram_component.address_b[3]
rdaddress[4] => altsyncram:altsyncram_component.address_b[4]
rdclock => altsyncram:altsyncram_component.clock1
wraddress[0] => altsyncram:altsyncram_component.address_a[0]
wraddress[1] => altsyncram:altsyncram_component.address_a[1]
wraddress[2] => altsyncram:altsyncram_component.address_a[2]
wraddress[3] => altsyncram:altsyncram_component.address_a[3]
wraddress[4] => altsyncram:altsyncram_component.address_a[4]
wrclock => altsyncram:altsyncram_component.clock0
wren => altsyncram:altsyncram_component.wren_a
q[0] <= altsyncram:altsyncram_component.q_b[0]
q[1] <= altsyncram:altsyncram_component.q_b[1]
q[2] <= altsyncram:altsyncram_component.q_b[2]
q[3] <= altsyncram:altsyncram_component.q_b[3]
q[4] <= altsyncram:altsyncram_component.q_b[4]
q[5] <= altsyncram:altsyncram_component.q_b[5]
q[6] <= altsyncram:altsyncram_component.q_b[6]
q[7] <= altsyncram:altsyncram_component.q_b[7]


|Vrms_ram_ctrl|Vrms_ram:Vrms_ram1|altsyncram:altsyncram_component
wren_a => altsyncram_26k1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_26k1:auto_generated.data_a[0]
data_a[1] => altsyncram_26k1:auto_generated.data_a[1]
data_a[2] => altsyncram_26k1:auto_generated.data_a[2]
data_a[3] => altsyncram_26k1:auto_generated.data_a[3]
data_a[4] => altsyncram_26k1:auto_generated.data_a[4]
data_a[5] => altsyncram_26k1:auto_generated.data_a[5]
data_a[6] => altsyncram_26k1:auto_generated.data_a[6]
data_a[7] => altsyncram_26k1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
address_a[0] => altsyncram_26k1:auto_generated.address_a[0]
address_a[1] => altsyncram_26k1:auto_generated.address_a[1]
address_a[2] => altsyncram_26k1:auto_generated.address_a[2]
address_a[3] => altsyncram_26k1:auto_generated.address_a[3]
address_a[4] => altsyncram_26k1:auto_generated.address_a[4]
address_b[0] => altsyncram_26k1:auto_generated.address_b[0]
address_b[1] => altsyncram_26k1:auto_generated.address_b[1]
address_b[2] => altsyncram_26k1:auto_generated.address_b[2]
address_b[3] => altsyncram_26k1:auto_generated.address_b[3]
address_b[4] => altsyncram_26k1:auto_generated.address_b[4]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_26k1:auto_generated.clock0
clock1 => altsyncram_26k1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_b[0] <= altsyncram_26k1:auto_generated.q_b[0]
q_b[1] <= altsyncram_26k1:auto_generated.q_b[1]
q_b[2] <= altsyncram_26k1:auto_generated.q_b[2]
q_b[3] <= altsyncram_26k1:auto_generated.q_b[3]
q_b[4] <= altsyncram_26k1:auto_generated.q_b[4]
q_b[5] <= altsyncram_26k1:auto_generated.q_b[5]
q_b[6] <= altsyncram_26k1:auto_generated.q_b[6]
q_b[7] <= altsyncram_26k1:auto_generated.q_b[7]
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|Vrms_ram_ctrl|Vrms_ram:Vrms_ram1|altsyncram:altsyncram_component|altsyncram_26k1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a7.ENA0