prev_cmp_vrms_ram_ctrl.map.qmsg

使用VHDL语言描述AD0809芯片功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 18 15:06:13 2008 " "Info: Processing started: Sun May 18 15:06:13 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Vrms_ram_ctrl -c Vrms_ram_ctrl " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Vrms_ram_ctrl -c Vrms_ram_ctrl" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../show_port_pack.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file ../show_port_pack.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 show_port_pack " "Info: Found design unit 1: show_port_pack" {  } { { "../show_port_pack.vhd" "" { Text "D:/new AD/show_port/show_port_pack.vhd" 4 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Vrms_ram.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Vrms_ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vrms_ram-SYN " "Info: Found design unit 1: vrms_ram-SYN" {  } { { "Vrms_ram.vhd" "" { Text "D:/new AD/show_port/Vrms_ram_ctrl/Vrms_ram.vhd" 56 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 Vrms_ram " "Info: Found entity 1: Vrms_ram" {  } { { "Vrms_ram.vhd" "" { Text "D:/new AD/show_port/Vrms_ram_ctrl/Vrms_ram.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../divide10_99.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../divide10_99.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divide10_99-SYN " "Info: Found design unit 1: divide10_99-SYN" {  } { { "../divide10_99.vhd" "" { Text "D:/new AD/show_port/divide10_99.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 divide10_99 " "Info: Found entity 1: divide10_99" {  } { { "../divide10_99.vhd" "" { Text "D:/new AD/show_port/divide10_99.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../divide10_999.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../divide10_999.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divide10_999-SYN " "Info: Found design unit 1: divide10_999-SYN" {  } { { "../divide10_999.vhd" "" { Text "D:/new AD/show_port/divide10_999.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 divide10_999 " "Info: Found entity 1: divide10_999" {  } { { "../divide10_999.vhd" "" { Text "D:/new AD/show_port/divide10_999.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Vrms_ram_ctrl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Vrms_ram_ctrl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Vrms_ram_ctrl-Vrms_ram_ctrl " "Info: Found design unit 1: Vrms_ram_ctrl-Vrms_ram_ctrl" {  } { { "Vrms_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vrms_ram_ctrl/Vrms_ram_ctrl.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 Vrms_ram_ctrl " "Info: Found entity 1: Vrms_ram_ctrl" {  } { { "Vrms_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vrms_ram_ctrl/Vrms_ram_ctrl.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "numer4 Vrms_ram_ctrl.vhd(82) " "Error (10482): VHDL error at Vrms_ram_ctrl.vhd(82): object \"numer4\" is used but not declared" {  } { { "Vrms_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vrms_ram_ctrl/Vrms_ram_ctrl.vhd" 82 0 0 } }  } 0 10482 "VHDL error at %2!s!: object \"%1!s!\" is used but not declared" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "154 " "Info: Allocated 154 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Sun May 18 15:06:14 2008 " "Error: Processing ended: Sun May 18 15:06:14 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}