📄 prev_cmp_adc_0820.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_state register register now_state.st8 rd_bar~reg0 340.02 MHz Internal " "Info: Clock \"clk_state\" Internal fmax is restricted to 340.02 MHz between source register \"now_state.st8\" and destination register \"rd_bar~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.244 ns + Longest register register " "Info: + Longest register to register delay is 1.244 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns now_state.st8 1 REG LCFF_X1_Y8_N13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y8_N13; Fanout = 4; REG Node = 'now_state.st8'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { now_state.st8 } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.485 ns) + CELL(0.651 ns) 1.136 ns Selector1~11 2 COMB LCCOMB_X1_Y8_N20 1 " "Info: 2: + IC(0.485 ns) + CELL(0.651 ns) = 1.136 ns; Loc. = LCCOMB_X1_Y8_N20; Fanout = 1; COMB Node = 'Selector1~11'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.136 ns" { now_state.st8 Selector1~11 } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 109 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.244 ns rd_bar~reg0 3 REG LCFF_X1_Y8_N21 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.244 ns; Loc. = LCFF_X1_Y8_N21; Fanout = 2; REG Node = 'rd_bar~reg0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Selector1~11 rd_bar~reg0 } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 103 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.759 ns ( 61.01 % ) " "Info: Total cell delay = 0.759 ns ( 61.01 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.485 ns ( 38.99 % ) " "Info: Total interconnect delay = 0.485 ns ( 38.99 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.244 ns" { now_state.st8 Selector1~11 rd_bar~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.244 ns" { now_state.st8 {} Selector1~11 {} rd_bar~reg0 {} } { 0.000ns 0.485ns 0.000ns } { 0.000ns 0.651ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_state destination 2.835 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_state\" to destination register is 2.835 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_state 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk_state'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_state } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk_state~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk_state~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk_state clk_state~clkctrl } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 2.835 ns rd_bar~reg0 3 REG LCFF_X1_Y8_N21 2 " "Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.835 ns; Loc. = LCFF_X1_Y8_N21; Fanout = 2; REG Node = 'rd_bar~reg0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.556 ns" { clk_state~clkctrl rd_bar~reg0 } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 103 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.70 % ) " "Info: Total cell delay = 1.806 ns ( 63.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.029 ns ( 36.30 % ) " "Info: Total interconnect delay = 1.029 ns ( 36.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.835 ns" { clk_state clk_state~clkctrl rd_bar~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.835 ns" { clk_state {} clk_state~combout {} clk_state~clkctrl {} rd_bar~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_state source 2.835 ns - Longest register " "Info: - Longest clock path from clock \"clk_state\" to source register is 2.835 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_state 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk_state'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_state } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk_state~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk_state~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk_state clk_state~clkctrl } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 2.835 ns now_state.st8 3 REG LCFF_X1_Y8_N13 4 " "Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.835 ns; Loc. = LCFF_X1_Y8_N13; Fanout = 4; REG Node = 'now_state.st8'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.556 ns" { clk_state~clkctrl now_state.st8 } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.70 % ) " "Info: Total cell delay = 1.806 ns ( 63.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.029 ns ( 36.30 % ) " "Info: Total interconnect delay = 1.029 ns ( 36.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.835 ns" { clk_state clk_state~clkctrl now_state.st8 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.835 ns" { clk_state {} clk_state~combout {} clk_state~clkctrl {} now_state.st8 {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.835 ns" { clk_state clk_state~clkctrl rd_bar~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.835 ns" { clk_state {} clk_state~combout {} clk_state~clkctrl {} rd_bar~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.835 ns" { clk_state clk_state~clkctrl now_state.st8 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.835 ns" { clk_state {} clk_state~combout {} clk_state~clkctrl {} now_state.st8 {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 26 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 103 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.244 ns" { now_state.st8 Selector1~11 rd_bar~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.244 ns" { now_state.st8 {} Selector1~11 {} rd_bar~reg0 {} } { 0.000ns 0.485ns 0.000ns } { 0.000ns 0.651ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.835 ns" { clk_state clk_state~clkctrl rd_bar~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.835 ns" { clk_state {} clk_state~combout {} clk_state~clkctrl {} rd_bar~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.835 ns" { clk_state clk_state~clkctrl now_state.st8 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.835 ns" { clk_state {} clk_state~combout {} clk_state~clkctrl {} now_state.st8 {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rd_bar~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { rd_bar~reg0 {} } { } { } "" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 103 0 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "now_state.st6 int_bar clk_state 4.160 ns register " "Info: tsu for register \"now_state.st6\" (data pin = \"int_bar\", clock pin = \"clk_state\") is 4.160 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.035 ns + Longest pin register " "Info: + Longest pin to register delay is 7.035 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns int_bar 1 PIN PIN_30 2 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_30; Fanout = 2; PIN Node = 'int_bar'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { int_bar } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.291 ns) + CELL(0.651 ns) 6.927 ns Selector8~10 2 COMB LCCOMB_X1_Y8_N10 1 " "Info: 2: + IC(5.291 ns) + CELL(0.651 ns) = 6.927 ns; Loc. = LCCOMB_X1_Y8_N10; Fanout = 1; COMB Node = 'Selector8~10'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.942 ns" { int_bar Selector8~10 } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 109 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.035 ns now_state.st6 3 REG LCFF_X1_Y8_N11 3 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.035 ns; Loc. = LCFF_X1_Y8_N11; Fanout = 3; REG Node = 'now_state.st6'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Selector8~10 now_state.st6 } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.744 ns ( 24.79 % ) " "Info: Total cell delay = 1.744 ns ( 24.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.291 ns ( 75.21 % ) " "Info: Total interconnect delay = 5.291 ns ( 75.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.035 ns" { int_bar Selector8~10 now_state.st6 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.035 ns" { int_bar {} int_bar~combout {} Selector8~10 {} now_state.st6 {} } { 0.000ns 0.000ns 5.291ns 0.000ns } { 0.000ns 0.985ns 0.651ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 26 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_state destination 2.835 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_state\" to destination register is 2.835 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_state 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk_state'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_state } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk_state~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk_state~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk_state clk_state~clkctrl } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 2.835 ns now_state.st6 3 REG LCFF_X1_Y8_N11 3 " "Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.835 ns; Loc. = LCFF_X1_Y8_N11; Fanout = 3; REG Node = 'now_state.st6'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.556 ns" { clk_state~clkctrl now_state.st6 } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.70 % ) " "Info: Total cell delay = 1.806 ns ( 63.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.029 ns ( 36.30 % ) " "Info: Total interconnect delay = 1.029 ns ( 36.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.835 ns" { clk_state clk_state~clkctrl now_state.st6 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.835 ns" { clk_state {} clk_state~combout {} clk_state~clkctrl {} now_state.st6 {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.035 ns" { int_bar Selector8~10 now_state.st6 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.035 ns" { int_bar {} int_bar~combout {} Selector8~10 {} now_state.st6 {} } { 0.000ns 0.000ns 5.291ns 0.000ns } { 0.000ns 0.985ns 0.651ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.835 ns" { clk_state clk_state~clkctrl now_state.st6 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.835 ns" { clk_state {} clk_state~combout {} clk_state~clkctrl {} now_state.st6 {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_state lock lock~reg0 7.632 ns register " "Info: tco from clock \"clk_state\" to destination pin \"lock\" through register \"lock~reg0\" is 7.632 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_state source 2.835 ns + Longest register " "Info: + Longest clock path from clock \"clk_state\" to source register is 2.835 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_state 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk_state'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_state } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk_state~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk_state~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk_state clk_state~clkctrl } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 2.835 ns lock~reg0 3 REG LCFF_X1_Y8_N9 2 " "Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.835 ns; Loc. = LCFF_X1_Y8_N9; Fanout = 2; REG Node = 'lock~reg0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.556 ns" { clk_state~clkctrl lock~reg0 } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 103 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.70 % ) " "Info: Total cell delay = 1.806 ns ( 63.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.029 ns ( 36.30 % ) " "Info: Total interconnect delay = 1.029 ns ( 36.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.835 ns" { clk_state clk_state~clkctrl lock~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.835 ns" { clk_state {} clk_state~combout {} clk_state~clkctrl {} lock~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 103 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.493 ns + Longest register pin " "Info: + Longest register to pin delay is 4.493 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lock~reg0 1 REG LCFF_X1_Y8_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y8_N9; Fanout = 2; REG Node = 'lock~reg0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lock~reg0 } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 103 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.387 ns) + CELL(3.106 ns) 4.493 ns lock 2 PIN PIN_14 0 " "Info: 2: + IC(1.387 ns) + CELL(3.106 ns) = 4.493 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'lock'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.493 ns" { lock~reg0 lock } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.106 ns ( 69.13 % ) " "Info: Total cell delay = 3.106 ns ( 69.13 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.387 ns ( 30.87 % ) " "Info: Total interconnect delay = 1.387 ns ( 30.87 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.493 ns" { lock~reg0 lock } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.493 ns" { lock~reg0 {} lock {} } { 0.000ns 1.387ns } { 0.000ns 3.106ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.835 ns" { clk_state clk_state~clkctrl lock~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.835 ns" { clk_state {} clk_state~combout {} clk_state~clkctrl {} lock~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.493 ns" { lock~reg0 lock } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.493 ns" { lock~reg0 {} lock {} } { 0.000ns 1.387ns } { 0.000ns 3.106ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "now_state.st7 int_bar clk_state -3.743 ns register " "Info: th for register \"now_state.st7\" (data pin = \"int_bar\", clock pin = \"clk_state\") is -3.743 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_state destination 2.835 ns + Longest register " "Info: + Longest clock path from clock \"clk_state\" to destination register is 2.835 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_state 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk_state'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_state } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk_state~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk_state~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk_state clk_state~clkctrl } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 2.835 ns now_state.st7 3 REG LCFF_X1_Y8_N31 3 " "Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.835 ns; Loc. = LCFF_X1_Y8_N31; Fanout = 3; REG Node = 'now_state.st7'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.556 ns" { clk_state~clkctrl now_state.st7 } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.70 % ) " "Info: Total cell delay = 1.806 ns ( 63.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.029 ns ( 36.30 % ) " "Info: Total interconnect delay = 1.029 ns ( 36.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.835 ns" { clk_state clk_state~clkctrl now_state.st7 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.835 ns" { clk_state {} clk_state~combout {} clk_state~clkctrl {} now_state.st7 {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 26 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.884 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.884 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns int_bar 1 PIN PIN_30 2 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_30; Fanout = 2; PIN Node = 'int_bar'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { int_bar } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.292 ns) + CELL(0.499 ns) 6.776 ns Selector9~15 2 COMB LCCOMB_X1_Y8_N30 1 " "Info: 2: + IC(5.292 ns) + CELL(0.499 ns) = 6.776 ns; Loc. = LCCOMB_X1_Y8_N30; Fanout = 1; COMB Node = 'Selector9~15'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.791 ns" { int_bar Selector9~15 } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 109 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.884 ns now_state.st7 3 REG LCFF_X1_Y8_N31 3 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.884 ns; Loc. = LCFF_X1_Y8_N31; Fanout = 3; REG Node = 'now_state.st7'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Selector9~15 now_state.st7 } "NODE_NAME" } } { "ADC_0820.vhd" "" { Text "D:/常用工具/优化大师/new AD/AD_port/AD_port_0820/ADC_0820/ADC_0820.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.592 ns ( 23.13 % ) " "Info: Total cell delay = 1.592 ns ( 23.13 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.292 ns ( 76.87 % ) " "Info: Total interconnect delay = 5.292 ns ( 76.87 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.884 ns" { int_bar Selector9~15 now_state.st7 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.884 ns" { int_bar {} int_bar~combout {} Selector9~15 {} now_state.st7 {} } { 0.000ns 0.000ns 5.292ns 0.000ns } { 0.000ns 0.985ns 0.499ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.835 ns" { clk_state clk_state~clkctrl now_state.st7 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.835 ns" { clk_state {} clk_state~combout {} clk_state~clkctrl {} now_state.st7 {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.884 ns" { int_bar Selector9~15 now_state.st7 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.884 ns" { int_bar {} int_bar~combout {} Selector9~15 {} now_state.st7 {} } { 0.000ns 0.000ns 5.292ns 0.000ns } { 0.000ns 0.985ns 0.499ns 0.108ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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