adc_0820.vho

使用VHDL语言描述AD0809芯片功能

	datain => \now_state.st1~6_combout\,
	aclr => \reset~clkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \now_state.st1~regout\);

\wr_bar~feeder\ : cycloneii_lcell_comb
-- Equation(s):
-- \wr_bar~feeder_combout\ = \now_state.st1~regout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \now_state.st1~regout\,
	combout => \wr_bar~feeder_combout\);

wr_bar : cycloneii_lcell_ff
PORT MAP (
	clk => \clk_state~clkctrl_outclk\,
	datain => \wr_bar~feeder_combout\,
	aclr => \reset~clkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \wr_bar~regout\);

\now_state.st3~feeder\ : cycloneii_lcell_comb
-- Equation(s):
-- \now_state.st3~feeder_combout\ = \wr_bar~regout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \wr_bar~regout\,
	combout => \now_state.st3~feeder_combout\);

\now_state.st3\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk_state~clkctrl_outclk\,
	datain => \now_state.st3~feeder_combout\,
	aclr => \reset~clkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \now_state.st3~regout\);

\now_state.st4~feeder\ : cycloneii_lcell_comb
-- Equation(s):
-- \now_state.st4~feeder_combout\ = \now_state.st3~regout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \now_state.st3~regout\,
	combout => \now_state.st4~feeder_combout\);

\now_state.st4\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk_state~clkctrl_outclk\,
	datain => \now_state.st4~feeder_combout\,
	aclr => \reset~clkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \now_state.st4~regout\);

\now_state.st5~feeder\ : cycloneii_lcell_comb
-- Equation(s):
-- \now_state.st5~feeder_combout\ = \now_state.st4~regout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \now_state.st4~regout\,
	combout => \now_state.st5~feeder_combout\);

\now_state.st5\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk_state~clkctrl_outclk\,
	datain => \now_state.st5~feeder_combout\,
	aclr => \reset~clkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \now_state.st5~regout\);

\Selector0~8\ : cycloneii_lcell_comb
-- Equation(s):
-- \Selector0~8_combout\ = \now_state.st5~regout\ # \int_bar~combout\ & \now_state.st6~regout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \int_bar~combout\,
	datac => \now_state.st6~regout\,
	datad => \now_state.st5~regout\,
	combout => \Selector0~8_combout\);

\now_state.st6\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk_state~clkctrl_outclk\,
	datain => \Selector0~8_combout\,
	aclr => \reset~clkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \now_state.st6~regout\);

\now_state~34\ : cycloneii_lcell_comb
-- Equation(s):
-- \now_state~34_combout\ = !\int_bar~combout\ & \now_state.st6~regout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101010100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \int_bar~combout\,
	datad => \now_state.st6~regout\,
	combout => \now_state~34_combout\);

\now_state.st7\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk_state~clkctrl_outclk\,
	datain => \now_state~34_combout\,
	aclr => \reset~clkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \now_state.st7~regout\);

\rd_bar~0\ : cycloneii_lcell_comb
-- Equation(s):
-- \rd_bar~0_combout\ = \now_state.st7~regout\ # \now_state.st6~regout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \now_state.st7~regout\,
	datad => \now_state.st6~regout\,
	combout => \rd_bar~0_combout\);

\rd_bar~reg0\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk_state~clkctrl_outclk\,
	datain => \rd_bar~0_combout\,
	aclr => \reset~clkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \rd_bar~reg0_regout\);

\lock~32\ : cycloneii_lcell_comb
-- Equation(s):
-- \lock~32_combout\ = \lock~reg0_regout\ # \now_state.st7~regout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \lock~reg0_regout\,
	datad => \now_state.st7~regout\,
	combout => \lock~32_combout\);

\lock~reg0\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk_state~clkctrl_outclk\,
	datain => \lock~32_combout\,
	aclr => \reset~clkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \lock~reg0_regout\);

\wr_rdy~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "bidir",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_wr_bar~regout\,
	oe => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	padio => wr_rdy);

\cs_bar~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_cs_bar);

\rd_bar~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_rd_bar~reg0_regout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_rd_bar);

\lock~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \lock~reg0_regout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_lock);
END structure;