vmax_ram_ctrl.tan.qmsg

用VHDL语言描述AD0809芯片

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "mem_read_clk memory memory Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|ram_block1a0~portb_address_reg0 Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|q_b\[0\] 163.03 MHz Internal " "Info: Clock \"mem_read_clk\" Internal fmax is restricted to 163.03 MHz between source memory \"Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|ram_block1a0~portb_address_reg0\" and destination memory \"Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|q_b\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "3.067 ns 3.067 ns 6.134 ns " "Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.639 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.639 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|ram_block1a0~portb_address_reg0 1 MEM M4K_X11_Y5 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X11_Y5; Fanout = 8; MEM Node = 'Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_g3q1.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/altsyncram_g3q1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.639 ns) 3.639 ns Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|q_b\[0\] 2 MEM M4K_X11_Y5 1 " "Info: 2: + IC(0.000 ns) + CELL(3.639 ns) = 3.639 ns; Loc. = M4K_X11_Y5; Fanout = 1; MEM Node = 'Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|q_b\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.639 ns" { Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~portb_address_reg0 Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|q_b[0] } "NODE_NAME" } } { "db/altsyncram_g3q1.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/altsyncram_g3q1.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.639 ns ( 100.00 % ) " "Info: Total cell delay = 3.639 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.639 ns" { Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~portb_address_reg0 Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.639 ns" { Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~portb_address_reg0 {} Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|q_b[0] {} } { 0.000ns 0.000ns } { 0.000ns 3.639ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.057 ns - Smallest " "Info: - Smallest clock skew is -0.057 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mem_read_clk destination 2.937 ns + Shortest memory " "Info: + Shortest clock path from clock \"mem_read_clk\" to destination memory is 2.937 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns mem_read_clk 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'mem_read_clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mem_read_clk } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns mem_read_clk~clkctrl 2 COMB CLKCTRL_G1 13 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 13; COMB Node = 'mem_read_clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { mem_read_clk mem_read_clk~clkctrl } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.847 ns) + CELL(0.821 ns) 2.937 ns Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|q_b\[0\] 3 MEM M4K_X11_Y5 1 " "Info: 3: + IC(0.847 ns) + CELL(0.821 ns) = 2.937 ns; Loc. = M4K_X11_Y5; Fanout = 1; MEM Node = 'Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|q_b\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.668 ns" { mem_read_clk~clkctrl Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|q_b[0] } "NODE_NAME" } } { "db/altsyncram_g3q1.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/altsyncram_g3q1.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.951 ns ( 66.43 % ) " "Info: Total cell delay = 1.951 ns ( 66.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.986 ns ( 33.57 % ) " "Info: Total interconnect delay = 0.986 ns ( 33.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.937 ns" { mem_read_clk mem_read_clk~clkctrl Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.937 ns" { mem_read_clk {} mem_read_clk~combout {} mem_read_clk~clkctrl {} Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|q_b[0] {} } { 0.000ns 0.000ns 0.139ns 0.847ns } { 0.000ns 1.130ns 0.000ns 0.821ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mem_read_clk source 2.994 ns - Longest memory " "Info: - Longest clock path from clock \"mem_read_clk\" to source memory is 2.994 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns mem_read_clk 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'mem_read_clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mem_read_clk } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns mem_read_clk~clkctrl 2 COMB CLKCTRL_G1 13 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 13; COMB Node = 'mem_read_clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { mem_read_clk mem_read_clk~clkctrl } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.847 ns) + CELL(0.878 ns) 2.994 ns Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|ram_block1a0~portb_address_reg0 3 MEM M4K_X11_Y5 8 " "Info: 3: + IC(0.847 ns) + CELL(0.878 ns) = 2.994 ns; Loc. = M4K_X11_Y5; Fanout = 8; MEM Node = 'Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.725 ns" { mem_read_clk~clkctrl Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_g3q1.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/altsyncram_g3q1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.008 ns ( 67.07 % ) " "Info: Total cell delay = 2.008 ns ( 67.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.986 ns ( 32.93 % ) " "Info: Total interconnect delay = 0.986 ns ( 32.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.994 ns" { mem_read_clk mem_read_clk~clkctrl Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.994 ns" { mem_read_clk {} mem_read_clk~combout {} mem_read_clk~clkctrl {} Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.847ns } { 0.000ns 1.130ns 0.000ns 0.878ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.937 ns" { mem_read_clk mem_read_clk~clkctrl Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.937 ns" { mem_read_clk {} mem_read_clk~combout {} mem_read_clk~clkctrl {} Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|q_b[0] {} } { 0.000ns 0.000ns 0.139ns 0.847ns } { 0.000ns 1.130ns 0.000ns 0.821ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.994 ns" { mem_read_clk mem_read_clk~clkctrl Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.994 ns" { mem_read_clk {} mem_read_clk~combout {} mem_read_clk~clkctrl {} Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.847ns } { 0.000ns 1.130ns 0.000ns 0.878ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_g3q1.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/altsyncram_g3q1.tdf" 38 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_g3q1.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/altsyncram_g3q1.tdf" 34 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.639 ns" { Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~portb_address_reg0 Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.639 ns" { Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~portb_address_reg0 {} Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|q_b[0] {} } { 0.000ns 0.000ns } { 0.000ns 3.639ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.937 ns" { mem_read_clk mem_read_clk~clkctrl Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.937 ns" { mem_read_clk {} mem_read_clk~combout {} mem_read_clk~clkctrl {} Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|q_b[0] {} } { 0.000ns 0.000ns 0.139ns 0.847ns } { 0.000ns 1.130ns 0.000ns 0.821ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.994 ns" { mem_read_clk mem_read_clk~clkctrl Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.994 ns" { mem_read_clk {} mem_read_clk~combout {} mem_read_clk~clkctrl {} Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.847ns } { 0.000ns 1.130ns 0.000ns 0.878ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|q_b[0] {} } { 0.000ns } { 0.109ns } "" } } { "db/altsyncram_g3q1.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/altsyncram_g3q1.tdf" 34 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_32k register memory mem_write_addr\[1\] Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|ram_block1a0~porta_datain_reg1 163.03 MHz Internal " "Info: Clock \"clk_32k\" Internal fmax is restricted to 163.03 MHz between source register \"mem_write_addr\[1\]\" and destination memory \"Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|ram_block1a0~porta_datain_reg1\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "3.067 ns 3.067 ns 6.134 ns " "Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.618 ns + Longest register memory " "Info: + Longest register to memory delay is 5.618 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mem_write_addr\[1\] 1 REG LCFF_X12_Y5_N15 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y5_N15; Fanout = 7; REG Node = 'mem_write_addr\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mem_write_addr[1] } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.202 ns) 0.874 ns Mux6~171 2 COMB LCCOMB_X12_Y5_N30 7 " "Info: 2: + IC(0.672 ns) + CELL(0.202 ns) = 0.874 ns; Loc. = LCCOMB_X12_Y5_N30; Fanout = 7; COMB Node = 'Mux6~171'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.874 ns" { mem_write_addr[1] Mux6~171 } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.624 ns) 2.563 ns Mux5~74 3 COMB LCCOMB_X13_Y5_N30 1 " "Info: 3: + IC(1.065 ns) + CELL(0.624 ns) = 2.563 ns; Loc. = LCCOMB_X13_Y5_N30; Fanout = 1; COMB Node = 'Mux5~74'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.689 ns" { Mux6~171 Mux5~74 } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.206 ns) 3.142 ns Mux5~75 4 COMB LCCOMB_X13_Y5_N12 1 " "Info: 4: + IC(0.373 ns) + CELL(0.206 ns) = 3.142 ns; Loc. = LCCOMB_X13_Y5_N12; Fanout = 1; COMB Node = 'Mux5~75'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.579 ns" { Mux5~74 Mux5~75 } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.360 ns) + CELL(0.206 ns) 3.708 ns Mux5~76 5 COMB LCCOMB_X13_Y5_N0 1 " "Info: 5: + IC(0.360 ns) + CELL(0.206 ns) = 3.708 ns; Loc. = LCCOMB_X13_Y5_N0; Fanout = 1; COMB Node = 'Mux5~76'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.566 ns" { Mux5~75 Mux5~76 } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.206 ns) 4.277 ns Mux5~77 6 COMB LCCOMB_X13_Y5_N20 1 " "Info: 6: + IC(0.363 ns) + CELL(0.206 ns) = 4.277 ns; Loc. = LCCOMB_X13_Y5_N20; Fanout = 1; COMB Node = 'Mux5~77'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.569 ns" { Mux5~76 Mux5~77 } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.213 ns) + CELL(0.128 ns) 5.618 ns Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|ram_block1a0~porta_datain_reg1 7 MEM M4K_X11_Y5 1 " "Info: 7: + IC(1.213 ns) + CELL(0.128 ns) = 5.618 ns; Loc. = M4K_X11_Y5; Fanout = 1; MEM Node = 'Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|ram_block1a0~porta_datain_reg1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.341 ns" { Mux5~77 Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~porta_datain_reg1 } "NODE_NAME" } } { "db/altsyncram_g3q1.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/altsyncram_g3q1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.572 ns ( 27.98 % ) " "Info: Total cell delay = 1.572 ns ( 27.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.046 ns ( 72.02 % ) " "Info: Total interconnect delay = 4.046 ns ( 72.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.618 ns" { mem_write_addr[1] Mux6~171 Mux5~74 Mux5~75 Mux5~76 Mux5~77 Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~porta_datain_reg1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.618 ns" { mem_write_addr[1] {} Mux6~171 {} Mux5~74 {} Mux5~75 {} Mux5~76 {} Mux5~77 {} Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~porta_datain_reg1 {} } { 0.000ns 0.672ns 1.065ns 0.373ns 0.360ns 0.363ns 1.213ns } { 0.000ns 0.202ns 0.624ns 0.206ns 0.206ns 0.206ns 0.128ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.088 ns - Smallest " "Info: - Smallest clock skew is 0.088 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_32k destination 2.960 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk_32k\" to destination memory is 2.960 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_32k 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk_32k'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_32k } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk_32k~clkctrl 2 COMB CLKCTRL_G2 27 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 27; COMB Node = 'clk_32k~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk_32k clk_32k~clkctrl } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.847 ns) + CELL(0.834 ns) 2.960 ns Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|ram_block1a0~porta_datain_reg1 3 MEM M4K_X11_Y5 1 " "Info: 3: + IC(0.847 ns) + CELL(0.834 ns) = 2.960 ns; Loc. = M4K_X11_Y5; Fanout = 1; MEM Node = 'Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|ram_block1a0~porta_datain_reg1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.681 ns" { clk_32k~clkctrl Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~porta_datain_reg1 } "NODE_NAME" } } { "db/altsyncram_g3q1.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/altsyncram_g3q1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.974 ns ( 66.69 % ) " "Info: Total cell delay = 1.974 ns ( 66.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.986 ns ( 33.31 % ) " "Info: Total interconnect delay = 0.986 ns ( 33.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.960 ns" { clk_32k clk_32k~clkctrl Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~porta_datain_reg1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.960 ns" { clk_32k {} clk_32k~combout {} clk_32k~clkctrl {} Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~porta_datain_reg1 {} } { 0.000ns 0.000ns 0.139ns 0.847ns } { 0.000ns 1.140ns 0.000ns 0.834ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_32k source 2.872 ns - Longest register " "Info: - Longest clock path from clock \"clk_32k\" to source register is 2.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_32k 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk_32k'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_32k } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk_32k~clkctrl 2 COMB CLKCTRL_G2 27 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 27; COMB Node = 'clk_32k~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk_32k clk_32k~clkctrl } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.927 ns) + CELL(0.666 ns) 2.872 ns mem_write_addr\[1\] 3 REG LCFF_X12_Y5_N15 7 " "Info: 3: + IC(0.927 ns) + CELL(0.666 ns) = 2.872 ns; Loc. = LCFF_X12_Y5_N15; Fanout = 7; REG Node = 'mem_write_addr\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.593 ns" { clk_32k~clkctrl mem_write_addr[1] } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.88 % ) " "Info: Total cell delay = 1.806 ns ( 62.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 37.12 % ) " "Info: Total interconnect delay = 1.066 ns ( 37.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { clk_32k clk_32k~clkctrl mem_write_addr[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { clk_32k {} clk_32k~combout {} clk_32k~clkctrl {} mem_write_addr[1] {} } { 0.000ns 0.000ns 0.139ns 0.927ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.960 ns" { clk_32k clk_32k~clkctrl Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~porta_datain_reg1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.960 ns" { clk_32k {} clk_32k~combout {} clk_32k~clkctrl {} Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~porta_datain_reg1 {} } { 0.000ns 0.000ns 0.139ns 0.847ns } { 0.000ns 1.140ns 0.000ns 0.834ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { clk_32k clk_32k~clkctrl mem_write_addr[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { clk_32k {} clk_32k~combout {} clk_32k~clkctrl {} mem_write_addr[1] {} } { 0.000ns 0.000ns 0.139ns 0.927ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 77 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_g3q1.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/altsyncram_g3q1.tdf" 38 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.618 ns" { mem_write_addr[1] Mux6~171 Mux5~74 Mux5~75 Mux5~76 Mux5~77 Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~porta_datain_reg1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.618 ns" { mem_write_addr[1] {} Mux6~171 {} Mux5~74 {} Mux5~75 {} Mux5~76 {} Mux5~77 {} Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~porta_datain_reg1 {} } { 0.000ns 0.672ns 1.065ns 0.373ns 0.360ns 0.363ns 1.213ns } { 0.000ns 0.202ns 0.624ns 0.206ns 0.206ns 0.206ns 0.128ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.960 ns" { clk_32k clk_32k~clkctrl Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~porta_datain_reg1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.960 ns" { clk_32k {} clk_32k~combout {} clk_32k~clkctrl {} Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~porta_datain_reg1 {} } { 0.000ns 0.000ns 0.139ns 0.847ns } { 0.000ns 1.140ns 0.000ns 0.834ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { clk_32k clk_32k~clkctrl mem_write_addr[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { clk_32k {} clk_32k~combout {} clk_32k~clkctrl {} mem_write_addr[1] {} } { 0.000ns 0.000ns 0.139ns 0.927ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~porta_datain_reg1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a0~porta_datain_reg1 {} } {  } {  } "" } } { "db/altsyncram_g3q1.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/altsyncram_g3q1.tdf" 38 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}