prev_cmp_vmax_ram_ctrl.fit.qmsg

用VHDL语言描述AD0809芯片

{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "28 unused 3.30 20 8 0 " "Info: Number of I/O pins in group: 28 (unused VREF, 3.30 VCCIO, 20 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 28 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  28 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  35 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  34 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  36 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.581 ns register memory " "Info: Estimated most critical path is register to memory delay of 6.581 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mem_write_addr\[2\] 1 REG LAB_X12_Y5 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y5; Fanout = 18; REG Node = 'mem_write_addr\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mem_write_addr[2] } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.511 ns) + CELL(0.370 ns) 0.881 ns Mux6~172 2 COMB LAB_X12_Y5 4 " "Info: 2: + IC(0.511 ns) + CELL(0.370 ns) = 0.881 ns; Loc. = LAB_X12_Y5; Fanout = 4; COMB Node = 'Mux6~172'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.881 ns" { mem_write_addr[2] Mux6~172 } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.911 ns) + CELL(0.206 ns) 1.998 ns Mux5~73 3 COMB LAB_X13_Y5 1 " "Info: 3: + IC(0.911 ns) + CELL(0.206 ns) = 1.998 ns; Loc. = LAB_X13_Y5; Fanout = 1; COMB Node = 'Mux5~73'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.117 ns" { Mux6~172 Mux5~73 } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.206 ns) 2.809 ns Mux5~74 4 COMB LAB_X13_Y5 1 " "Info: 4: + IC(0.605 ns) + CELL(0.206 ns) = 2.809 ns; Loc. = LAB_X13_Y5; Fanout = 1; COMB Node = 'Mux5~74'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { Mux5~73 Mux5~74 } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.187 ns) + CELL(0.624 ns) 3.620 ns Mux5~75 5 COMB LAB_X13_Y5 1 " "Info: 5: + IC(0.187 ns) + CELL(0.624 ns) = 3.620 ns; Loc. = LAB_X13_Y5; Fanout = 1; COMB Node = 'Mux5~75'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { Mux5~74 Mux5~75 } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.366 ns) 4.427 ns Mux5~76 6 COMB LAB_X13_Y5 1 " "Info: 6: + IC(0.441 ns) + CELL(0.366 ns) = 4.427 ns; Loc. = LAB_X13_Y5; Fanout = 1; COMB Node = 'Mux5~76'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.807 ns" { Mux5~75 Mux5~76 } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.370 ns) 5.238 ns Mux5~77 7 COMB LAB_X13_Y5 1 " "Info: 7: + IC(0.441 ns) + CELL(0.370 ns) = 5.238 ns; Loc. = LAB_X13_Y5; Fanout = 1; COMB Node = 'Mux5~77'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { Mux5~76 Mux5~77 } "NODE_NAME" } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.215 ns) + CELL(0.128 ns) 6.581 ns Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|ram_block1a1~porta_datain_reg0 8 MEM M4K_X11_Y5 1 " "Info: 8: + IC(1.215 ns) + CELL(0.128 ns) = 6.581 ns; Loc. = M4K_X11_Y5; Fanout = 1; MEM Node = 'Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\|ram_block1a1~porta_datain_reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.343 ns" { Mux5~77 Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a1~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_g3q1.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/altsyncram_g3q1.tdf" 70 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.270 ns ( 34.49 % ) " "Info: Total cell delay = 2.270 ns ( 34.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.311 ns ( 65.51 % ) " "Info: Total interconnect delay = 4.311 ns ( 65.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.581 ns" { mem_write_addr[2] Mux6~172 Mux5~73 Mux5~74 Mux5~75 Mux5~76 Mux5~77 Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated|ram_block1a1~porta_datain_reg0 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}