vmax_ram_ctrl.hif

用VHDL语言描述AD0809芯片

USR
}
# hierarchies {
divide10_99:divide10_99a
}
# lmf
..|..|..|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
lpm_divide
# storage
db|Vmax_ram_ctrl.(18).cnf
db|Vmax_ram_ctrl.(18).cnf
# case_insensitive
# source_file
..|..|..|altera|72|quartus|libraries|megafunctions|lpm_divide.tdf
706ba3e8b43cbca887f6dcfbde4d7290
6
# user_parameter {
LPM_WIDTHN
7
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHD
4
PARAMETER_SIGNED_DEC
USR
LPM_NREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
LPM_REMAINDERPOSITIVE
TRUE
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
lpm_divide_frp
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
remain3
-1
3
remain2
-1
3
remain1
-1
3
remain0
-1
3
quotient6
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numer6
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom3
-1
3
denom2
-1
3
denom1
-1
3
denom0
-1
3
}
# include_file {
..|..|..|altera|72|quartus|libraries|megafunctions|aglobal72.inc
f39123b8592ab2dac019716e56b3ec18
..|..|..|altera|72|quartus|libraries|megafunctions|sign_div_unsign.inc
c1e17922387cb5d0c88d7fb673544bb4
..|..|..|altera|72|quartus|libraries|megafunctions|abs_divider.inc
cdfefd53e136b3a8e541899b82db37d
}
# hierarchies {
divide10_99:divide10_99a|lpm_divide:lpm_divide_component
}
# lmf
..|..|..|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
lpm_divide_frp
# storage
db|Vmax_ram_ctrl.(19).cnf
db|Vmax_ram_ctrl.(19).cnf
# case_insensitive
# source_file
db|lpm_divide_frp.tdf
9b92326b50955c333158f17db0567550
6
# used_port {
remain3
-1
3
remain2
-1
3
remain1
-1
3
remain0
-1
3
quotient6
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numer6
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom3
-1
3
denom2
-1
3
denom1
-1
3
denom0
-1
3
}
# hierarchies {
divide10_99:divide10_99a|lpm_divide:lpm_divide_component|lpm_divide_frp:auto_generated
}
# lmf
..|..|..|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
sign_div_unsign_akh
# storage
db|Vmax_ram_ctrl.(20).cnf
db|Vmax_ram_ctrl.(20).cnf
# case_insensitive
# source_file
db|sign_div_unsign_akh.tdf
74f14dad7d933c97235dc376dbafeec6
6
# used_port {
remainder3
-1
3
remainder2
-1
3
remainder1
-1
3
remainder0
-1
3
quotient6
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numerator6
-1
3
numerator5
-1
3
numerator4
-1
3
numerator3
-1
3
numerator2
-1
3
numerator1
-1
3
numerator0
-1
3
denominator3
-1
3
denominator2
-1
3
denominator1
-1
3
denominator0
-1
3
}
# hierarchies {
divide10_99:divide10_99a|lpm_divide:lpm_divide_component|lpm_divide_frp:auto_generated|sign_div_unsign_akh:divider
}
# lmf
..|..|..|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
alt_u_div_mve
# storage
db|Vmax_ram_ctrl.(21).cnf
db|Vmax_ram_ctrl.(21).cnf
# case_insensitive
# source_file
db|alt_u_div_mve.tdf
4cb3ca98b58e142987236f36c174930
6
# used_port {
remainder3
-1
3
remainder2
-1
3
remainder1
-1
3
remainder0
-1
3
quotient6
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numerator6
-1
3
numerator5
-1
3
numerator4
-1
3
numerator3
-1
3
numerator2
-1
3
numerator1
-1
3
numerator0
-1
3
denominator3
-1
3
denominator2
-1
3
denominator1
-1
3
denominator0
-1
3
}
# hierarchies {
divide10_99:divide10_99a|lpm_divide:lpm_divide_component|lpm_divide_frp:auto_generated|sign_div_unsign_akh:divider|alt_u_div_mve:divider
}
# lmf
..|..|..|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
Vmax_ram
# storage
db|Vmax_ram_ctrl.(22).cnf
db|Vmax_ram_ctrl.(22).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
Vmax_ram.vhd
e9a1aff432268f591a6af4f6924e97b
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(data)
7 downto 0
PARAMETER_STRING
USR
 constraint(rdaddress)
4 downto 0
PARAMETER_STRING
USR
 constraint(wraddress)
4 downto 0
PARAMETER_STRING
USR
 constraint(q)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
Vmax_ram:Vmax_ram1
}
# lmf
..|..|..|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
altsyncram
# storage
db|Vmax_ram_ctrl.(23).cnf
db|Vmax_ram_ctrl.(23).cnf
# case_insensitive
# source_file
..|..|..|altera|72|quartus|libraries|megafunctions|altsyncram.tdf
56e814d9f431d4c82859865aa9372
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
32
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
32
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
../../Program Files/altera/WORK/flip_flop/rom1/rom.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_g3q1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
..|..|..|altera|72|quartus|libraries|megafunctions|aglobal72.inc
f39123b8592ab2dac019716e56b3ec18
..|..|..|altera|72|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|altera|72|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|altera|72|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|altera|72|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|altera|72|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|altera|72|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|altera|72|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
..|..|..|altera|72|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component
}
# lmf
..|..|..|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
altsyncram_g3q1
# storage
db|Vmax_ram_ctrl.(24).cnf
db|Vmax_ram_ctrl.(24).cnf
# case_insensitive
# source_file
db|altsyncram_g3q1.tdf
406f5bb87a47927c083c9ee8bcbebf
6
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
..|..|Program Files|altera|WORK|flip_flop|rom1|rom.mif
0
}
# hierarchies {
Vmax_ram:Vmax_ram1|altsyncram:altsyncram_component|altsyncram_g3q1:auto_generated
}
# lmf
..|..|..|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
Vmax_ram_ctrl
# storage
db|Vmax_ram_ctrl.(0).cnf
db|Vmax_ram_ctrl.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
Vmax_ram_ctrl.vhd
cfc5ac7654fe7d6fe3ce49d2b8e9de5d
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# include_file {
..|show_port_pack.vhd
c83827b3179def495e1ff54f0fcc815
}
# hierarchies {
|
}
# lmf
..|..|..|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# complete