vmax_ram_ctrl.map.qmsg

用VHDL语言描述AD0809芯片

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_u_div_a2f divide10_999:divide10_999a\|lpm_divide:lpm_divide_component\|lpm_divide_psp:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_a2f:divider " "Info: Elaborating entity \"alt_u_div_a2f\" for hierarchy \"divide10_999:divide10_999a\|lpm_divide:lpm_divide_component\|lpm_divide_psp:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_a2f:divider\"" {  } { { "db/sign_div_unsign_klh.tdf" "divider" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/sign_div_unsign_klh.tdf" 32 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divide10_99 divide10_99:divide10_99a " "Info: Elaborating entity \"divide10_99\" for hierarchy \"divide10_99:divide10_99a\"" {  } { { "Vmax_ram_ctrl.vhd" "divide10_99a" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 66 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_divide divide10_99:divide10_99a\|lpm_divide:lpm_divide_component " "Info: Elaborating entity \"lpm_divide\" for hierarchy \"divide10_99:divide10_99a\|lpm_divide:lpm_divide_component\"" {  } { { "../divide10_99.vhd" "lpm_divide_component" { Text "D:/new AD/show_port/divide10_99.vhd" 81 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "divide10_99:divide10_99a\|lpm_divide:lpm_divide_component " "Info: Elaborated megafunction instantiation \"divide10_99:divide10_99a\|lpm_divide:lpm_divide_component\"" {  } { { "../divide10_99.vhd" "" { Text "D:/new AD/show_port/divide10_99.vhd" 81 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_frp.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_frp.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_frp " "Info: Found entity 1: lpm_divide_frp" {  } { { "db/lpm_divide_frp.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/lpm_divide_frp.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_divide_frp divide10_99:divide10_99a\|lpm_divide:lpm_divide_component\|lpm_divide_frp:auto_generated " "Info: Elaborating entity \"lpm_divide_frp\" for hierarchy \"divide10_99:divide10_99a\|lpm_divide:lpm_divide_component\|lpm_divide_frp:auto_generated\"" {  } { { "lpm_divide.tdf" "auto_generated" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf" 147 9 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_akh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_akh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_akh " "Info: Found entity 1: sign_div_unsign_akh" {  } { { "db/sign_div_unsign_akh.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/sign_div_unsign_akh.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign_div_unsign_akh divide10_99:divide10_99a\|lpm_divide:lpm_divide_component\|lpm_divide_frp:auto_generated\|sign_div_unsign_akh:divider " "Info: Elaborating entity \"sign_div_unsign_akh\" for hierarchy \"divide10_99:divide10_99a\|lpm_divide:lpm_divide_component\|lpm_divide_frp:auto_generated\|sign_div_unsign_akh:divider\"" {  } { { "db/lpm_divide_frp.tdf" "divider" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/lpm_divide_frp.tdf" 32 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_mve.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_mve.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_mve " "Info: Found entity 1: alt_u_div_mve" {  } { { "db/alt_u_div_mve.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/alt_u_div_mve.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_u_div_mve divide10_99:divide10_99a\|lpm_divide:lpm_divide_component\|lpm_divide_frp:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_mve:divider " "Info: Elaborating entity \"alt_u_div_mve\" for hierarchy \"divide10_99:divide10_99a\|lpm_divide:lpm_divide_component\|lpm_divide_frp:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_mve:divider\"" {  } { { "db/sign_div_unsign_akh.tdf" "divider" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/sign_div_unsign_akh.tdf" 32 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Vmax_ram Vmax_ram:Vmax_ram1 " "Info: Elaborating entity \"Vmax_ram\" for hierarchy \"Vmax_ram:Vmax_ram1\"" {  } { { "Vmax_ram_ctrl.vhd" "Vmax_ram1" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 113 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/72/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/72/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\"" {  } { { "Vmax_ram.vhd" "altsyncram_component" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram.vhd" 98 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\"" {  } { { "Vmax_ram.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram.vhd" 98 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g3q1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_g3q1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g3q1 " "Info: Found entity 1: altsyncram_g3q1" {  } { { "db/altsyncram_g3q1.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/altsyncram_g3q1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g3q1 Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated " "Info: Elaborating entity \"altsyncram_g3q1\" for hierarchy \"Vmax_ram:Vmax_ram1\|altsyncram:altsyncram_component\|altsyncram_g3q1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Info: Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "divide10_999:divide10_999a\|lpm_divide:lpm_divide_component\|lpm_divide_psp:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_a2f:divider\|add_sub_9_result_int\[0\]~12 " "Info (17048): Logic cell \"divide10_999:divide10_999a\|lpm_divide:lpm_divide_component\|lpm_divide_psp:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_a2f:divider\|add_sub_9_result_int\[0\]~12\"" {  } { { "db/alt_u_div_a2f.tdf" "add_sub_9_result_int\[0\]~12" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/alt_u_div_a2f.tdf" 72 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Found the following redundant logic cells in design" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "236 " "Info: Implemented 236 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Info: Implemented 22 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "198 " "Info: Implemented 198 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "169 " "Info: Allocated 169 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 18 14:34:52 2008 " "Info: Processing ended: Sun May 18 14:34:52 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}