vmax_ram_ctrl.map.qmsg

用VHDL语言描述AD0809芯片

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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/72/quartus/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/72/quartus/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf" 118 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_tsp.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_tsp.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_tsp " "Info: Found entity 1: lpm_divide_tsp" {  } { { "db/lpm_divide_tsp.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/lpm_divide_tsp.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_divide_tsp divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated " "Info: Elaborating entity \"lpm_divide_tsp\" for hierarchy \"divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\"" {  } { { "lpm_divide.tdf" "auto_generated" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf" 147 9 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_olh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_olh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_olh " "Info: Found entity 1: sign_div_unsign_olh" {  } { { "db/sign_div_unsign_olh.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/sign_div_unsign_olh.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign_div_unsign_olh divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\|sign_div_unsign_olh:divider " "Info: Elaborating entity \"sign_div_unsign_olh\" for hierarchy \"divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\|sign_div_unsign_olh:divider\"" {  } { { "db/lpm_divide_tsp.tdf" "divider" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/lpm_divide_tsp.tdf" 32 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_i2f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_i2f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_i2f " "Info: Found entity 1: alt_u_div_i2f" {  } { { "db/alt_u_div_i2f.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/alt_u_div_i2f.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_u_div_i2f divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider " "Info: Elaborating entity \"alt_u_div_i2f\" for hierarchy \"divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\"" {  } { { "db/sign_div_unsign_olh.tdf" "divider" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/sign_div_unsign_olh.tdf" 32 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lkc " "Info: Found entity 1: add_sub_lkc" {  } { { "db/add_sub_lkc.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/add_sub_lkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_lkc divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|add_sub_lkc:add_sub_0 " "Info: Elaborating entity \"add_sub_lkc\" for hierarchy \"divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|add_sub_lkc:add_sub_0\"" {  } { { "db/alt_u_div_i2f.tdf" "add_sub_0" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/alt_u_div_i2f.tdf" 35 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_mkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_mkc " "Info: Found entity 1: add_sub_mkc" {  } { { "db/add_sub_mkc.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/add_sub_mkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_mkc divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|add_sub_mkc:add_sub_1 " "Info: Elaborating entity \"add_sub_mkc\" for hierarchy \"divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|add_sub_mkc:add_sub_1\"" {  } { { "db/alt_u_div_i2f.tdf" "add_sub_1" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/alt_u_div_i2f.tdf" 36 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divide10_999 divide10_999:divide10_999a " "Info: Elaborating entity \"divide10_999\" for hierarchy \"divide10_999:divide10_999a\"" {  } { { "Vmax_ram_ctrl.vhd" "divide10_999a" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 59 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign_div_unsign_klh divide10_999:divide10_999a\|lpm_divide:lpm_divide_component\|lpm_divide_psp:auto_generated\|sign_div_unsign_klh:divider " "Info: Elaborating entity \"sign_div_unsign_klh\" for hierarchy \"divide10_999:divide10_999a\|lpm_divide:lpm_divide_component\|lpm_divide_psp:auto_generated\|sign_div_unsign_klh:divider\"" {  } { { "db/lpm_divide_psp.tdf" "divider" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/lpm_divide_psp.tdf" 32 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_a2f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_a2f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_a2f " "Info: Found entity 1: alt_u_div_a2f" {  } { { "db/alt_u_div_a2f.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/alt_u_div_a2f.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}