vmax_ram_ctrl.map.qmsg

用VHDL语言描述AD0809芯片

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 18 14:34:47 2008 " "Info: Processing started: Sun May 18 14:34:47 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Vmax_ram_ctrl -c Vmax_ram_ctrl " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Vmax_ram_ctrl -c Vmax_ram_ctrl" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../divide10_99.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../divide10_99.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divide10_99-SYN " "Info: Found design unit 1: divide10_99-SYN" {  } { { "../divide10_99.vhd" "" { Text "D:/new AD/show_port/divide10_99.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 divide10_99 " "Info: Found entity 1: divide10_99" {  } { { "../divide10_99.vhd" "" { Text "D:/new AD/show_port/divide10_99.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../divide10_999.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../divide10_999.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divide10_999-SYN " "Info: Found design unit 1: divide10_999-SYN" {  } { { "../divide10_999.vhd" "" { Text "D:/new AD/show_port/divide10_999.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 divide10_999 " "Info: Found entity 1: divide10_999" {  } { { "../divide10_999.vhd" "" { Text "D:/new AD/show_port/divide10_999.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../divide10_9999.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../divide10_9999.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divide10_9999-SYN " "Info: Found design unit 1: divide10_9999-SYN" {  } { { "../divide10_9999.vhd" "" { Text "D:/new AD/show_port/divide10_9999.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 divide10_9999 " "Info: Found entity 1: divide10_9999" {  } { { "../divide10_9999.vhd" "" { Text "D:/new AD/show_port/divide10_9999.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../abs_9999.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../abs_9999.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 abs_9999-SYN " "Info: Found design unit 1: abs_9999-SYN" {  } { { "../abs_9999.vhd" "" { Text "D:/new AD/show_port/abs_9999.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 abs_9999 " "Info: Found entity 1: abs_9999" {  } { { "../abs_9999.vhd" "" { Text "D:/new AD/show_port/abs_9999.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Vmax_ram.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Vmax_ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vmax_ram-SYN " "Info: Found design unit 1: vmax_ram-SYN" {  } { { "Vmax_ram.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram.vhd" 56 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 Vmax_ram " "Info: Found entity 1: Vmax_ram" {  } { { "Vmax_ram.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Vmax_ram_ctrl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Vmax_ram_ctrl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Vmax_ram_ctrl-Vmax_ram_ctrl " "Info: Found design unit 1: Vmax_ram_ctrl-Vmax_ram_ctrl" {  } { { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 Vmax_ram_ctrl " "Info: Found entity 1: Vmax_ram_ctrl" {  } { { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../show_port_pack.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file ../show_port_pack.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 show_port_pack " "Info: Found design unit 1: show_port_pack" {  } { { "../show_port_pack.vhd" "" { Text "D:/new AD/show_port/show_port_pack.vhd" 4 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Vmax_ram_ctrl " "Info: Elaborating entity \"Vmax_ram_ctrl\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "abs_9999 abs_9999:abs_9999a " "Info: Elaborating entity \"abs_9999\" for hierarchy \"abs_9999:abs_9999a\"" {  } { { "Vmax_ram_ctrl.vhd" "abs_9999a" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 47 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/72/quartus/libraries/megafunctions/lpm_abs.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/72/quartus/libraries/megafunctions/lpm_abs.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs " "Info: Found entity 1: lpm_abs" {  } { { "lpm_abs.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_abs.tdf" 39 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_abs abs_9999:abs_9999a\|lpm_abs:lpm_abs_component " "Info: Elaborating entity \"lpm_abs\" for hierarchy \"abs_9999:abs_9999a\|lpm_abs:lpm_abs_component\"" {  } { { "../abs_9999.vhd" "lpm_abs_component" { Text "D:/new AD/show_port/abs_9999.vhd" 71 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "abs_9999:abs_9999a\|lpm_abs:lpm_abs_component " "Info: Elaborated megafunction instantiation \"abs_9999:abs_9999a\|lpm_abs:lpm_abs_component\"" {  } { { "../abs_9999.vhd" "" { Text "D:/new AD/show_port/abs_9999.vhd" 71 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub abs_9999:abs_9999a\|lpm_abs:lpm_abs_component\|lpm_add_sub:adder " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"abs_9999:abs_9999a\|lpm_abs:lpm_abs_component\|lpm_add_sub:adder\"" {  } { { "lpm_abs.tdf" "adder" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_abs.tdf" 54 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "abs_9999:abs_9999a\|lpm_abs:lpm_abs_component\|lpm_add_sub:adder abs_9999:abs_9999a\|lpm_abs:lpm_abs_component " "Info: Elaborated megafunction instantiation \"abs_9999:abs_9999a\|lpm_abs:lpm_abs_component\|lpm_add_sub:adder\", which is child of megafunction instantiation \"abs_9999:abs_9999a\|lpm_abs:lpm_abs_component\"" {  } { { "lpm_abs.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_abs.tdf" 54 4 0 } } { "../abs_9999.vhd" "" { Text "D:/new AD/show_port/abs_9999.vhd" 71 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "abs_9999:abs_9999a\|lpm_abs:lpm_abs_component " "Info: Instantiated megafunction \"abs_9999:abs_9999a\|lpm_abs:lpm_abs_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ABS " "Info: Parameter \"lpm_type\" = \"LPM_ABS\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 15 " "Info: Parameter \"lpm_width\" = \"15\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "../abs_9999.vhd" "" { Text "D:/new AD/show_port/abs_9999.vhd" 71 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_itc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_itc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_itc " "Info: Found entity 1: add_sub_itc" {  } { { "db/add_sub_itc.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/add_sub_itc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_itc abs_9999:abs_9999a\|lpm_abs:lpm_abs_component\|lpm_add_sub:adder\|add_sub_itc:auto_generated " "Info: Elaborating entity \"add_sub_itc\" for hierarchy \"abs_9999:abs_9999a\|lpm_abs:lpm_abs_component\|lpm_add_sub:adder\|add_sub_itc:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "datab " "Warning: Variable or input pin \"datab\" is defined but never used" {  } { { "db/add_sub_itc.tdf" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/db/add_sub_itc.tdf" 26 2 0 } } { "lpm_add_sub.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } { "lpm_abs.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_abs.tdf" 54 4 0 } } { "../abs_9999.vhd" "" { Text "D:/new AD/show_port/abs_9999.vhd" 71 0 0 } } { "Vmax_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/Vmax_ram_ctrl/Vmax_ram_ctrl.vhd" 79 0 0 } }  } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0}