i2c_testdevice.fit.qmsg

I2C slave可以作動

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.173 ns register register " "Info: Estimated most critical path is register to register delay of 7.173 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|scl_sampled\[1\] 1 REG LAB_X25_Y15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X25_Y15; Fanout = 4; REG Node = 'pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|scl_sampled\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[1] } "NODE_NAME" } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 150 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.668 ns) + CELL(0.114 ns) 0.782 ns pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|Equal8~55 2 COMB LAB_X25_Y15 6 " "Info: 2: + IC(0.668 ns) + CELL(0.114 ns) = 0.782 ns; Loc. = LAB_X25_Y15; Fanout = 6; COMB Node = 'pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|Equal8~55'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.782 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[1] pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Equal8~55 } "NODE_NAME" } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 1.435 ns pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|Selector19~56 3 COMB LAB_X25_Y15 2 " "Info: 3: + IC(0.539 ns) + CELL(0.114 ns) = 1.435 ns; Loc. = LAB_X25_Y15; Fanout = 2; COMB Node = 'pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|Selector19~56'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Equal8~55 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Selector19~56 } "NODE_NAME" } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 225 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.514 ns) + CELL(0.292 ns) 4.241 ns pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|write_state~1306 4 COMB LAB_X13_Y9 2 " "Info: 4: + IC(2.514 ns) + CELL(0.292 ns) = 4.241 ns; Loc. = LAB_X13_Y9; Fanout = 2; COMB Node = 'pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|write_state~1306'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.806 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Selector19~56 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state~1306 } "NODE_NAME" } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 125 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.194 ns) + CELL(0.738 ns) 7.173 ns pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|write_state.wait_scl_rising 5 REG LAB_X24_Y14 33 " "Info: 5: + IC(2.194 ns) + CELL(0.738 ns) = 7.173 ns; Loc. = LAB_X24_Y14; Fanout = 33; REG Node = 'pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|write_state.wait_scl_rising'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.932 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state~1306 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state.wait_scl_rising } "NODE_NAME" } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 224 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.258 ns ( 17.54 % ) " "Info: Total cell delay = 1.258 ns ( 17.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.915 ns ( 82.46 % ) " "Info: Total interconnect delay = 5.915 ns ( 82.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.173 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[1] pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Equal8~55 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Selector19~56 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state~1306 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state.wait_scl_rising } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 5 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 5%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x24_y11 x35_y21 " "Info: The peak interconnect region extends from location x24_y11 to location x35_y21" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|sda_out " "Info: Following pins have the same output enable: pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|sda_out" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sda LVTTL " "Info: Type bidirectional pin sda uses the LVTTL I/O standard" {  } { { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 17 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sda" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sda } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sda } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 28 02:36:22 2006 " "Info: Processing ended: Sat Oct 28 02:36:22 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}