i2c_testdevice.map.qmsg

I2C slave可以作動

{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "pca9555:pca9555_instance\|comb~4 " "Warning: Converting TRI node \"pca9555:pca9555_instance\|comb~4\" that feeds logic to an OR gate" {  } {  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "pca9555:pca9555_instance\|comb~3 " "Warning: Converting TRI node \"pca9555:pca9555_instance\|comb~3\" that feeds logic to an OR gate" {  } {  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "pca9555:pca9555_instance\|comb~2 " "Warning: Converting TRI node \"pca9555:pca9555_instance\|comb~2\" that feeds logic to an OR gate" {  } {  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "pca9555:pca9555_instance\|comb~1 " "Warning: Converting TRI node \"pca9555:pca9555_instance\|comb~1\" that feeds logic to an OR gate" {  } {  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "pca9555:pca9555_instance\|comb~0 " "Warning: Converting TRI node \"pca9555:pca9555_instance\|comb~0\" that feeds logic to an OR gate" {  } {  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "pca9555:pca9555_instance\|comb~6 " "Warning: Converting TRI node \"pca9555:pca9555_instance\|comb~6\" that feeds logic to an OR gate" {  } {  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "pca9555:pca9555_instance\|comb~7 " "Warning: Converting TRI node \"pca9555:pca9555_instance\|comb~7\" that feeds logic to an OR gate" {  } {  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "port0\[7\]~0 " "Warning: Removed always-enabled tri-state buffer port0\[7\]~0 feeding logic, open-drain buffer, or output pin" {  } { { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 42 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "port0\[6\]~1 " "Warning: Removed always-enabled tri-state buffer port0\[6\]~1 feeding logic, open-drain buffer, or output pin" {  } { { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 42 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "port0\[5\]~2 " "Warning: Removed always-enabled tri-state buffer port0\[5\]~2 feeding logic, open-drain buffer, or output pin" {  } { { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 42 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "port0\[4\]~3 " "Warning: Removed always-enabled tri-state buffer port0\[4\]~3 feeding logic, open-drain buffer, or output pin" {  } { { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 42 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "port0\[3\]~4 " "Warning: Removed always-enabled tri-state buffer port0\[3\]~4 feeding logic, open-drain buffer, or output pin" {  } { { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 42 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "port0\[2\]~5 " "Warning: Removed always-enabled tri-state buffer port0\[2\]~5 feeding logic, open-drain buffer, or output pin" {  } { { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 42 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "port0\[1\]~6 " "Warning: Removed always-enabled tri-state buffer port0\[1\]~6 feeding logic, open-drain buffer, or output pin" {  } { { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 42 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "port0\[0\]~7 " "Warning: Removed always-enabled tri-state buffer port0\[0\]~7 feeding logic, open-drain buffer, or output pin" {  } { { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 42 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 150 -1 0 } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 150 -1 0 } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 150 -1 0 } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 150 -1 0 } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 150 -1 0 } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 150 -1 0 } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 150 -1 0 } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 150 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "316 " "Info: Implemented 316 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "296 " "Info: Implemented 296 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 32 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 28 02:36:08 2006 " "Info: Processing ended: Sat Oct 28 02:36:08 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}