i2c_testdevice.tan.qmsg

I2C slave可以作動

{ "Info" "ITDB_FULL_TCO_RESULT" "clock_50mhz led\[0\] pca9555:pca9555_instance\|port1\[0\]~en 10.177 ns register " "Info: tco from clock \"clock_50mhz\" to destination pin \"led\[0\]\" through register \"pca9555:pca9555_instance\|port1\[0\]~en\" is 10.177 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_50mhz source 2.944 ns + Longest register " "Info: + Longest clock path from clock \"clock_50mhz\" to source register is 2.944 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_50mhz 1 CLK PIN_28 181 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 181; CLK Node = 'clock_50mhz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock_50mhz } "NODE_NAME" } } { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.764 ns) + CELL(0.711 ns) 2.944 ns pca9555:pca9555_instance\|port1\[0\]~en 2 REG LC_X27_Y12_N3 2 " "Info: 2: + IC(0.764 ns) + CELL(0.711 ns) = 2.944 ns; Loc. = LC_X27_Y12_N3; Fanout = 2; REG Node = 'pca9555:pca9555_instance\|port1\[0\]~en'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.475 ns" { clock_50mhz pca9555:pca9555_instance|port1[0]~en } "NODE_NAME" } } { "../../rtl/vhdl/pca9555.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/pca9555.vhdl" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.05 % ) " "Info: Total cell delay = 2.180 ns ( 74.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.764 ns ( 25.95 % ) " "Info: Total interconnect delay = 0.764 ns ( 25.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.944 ns" { clock_50mhz pca9555:pca9555_instance|port1[0]~en } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.944 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|port1[0]~en } { 0.000ns 0.000ns 0.764ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../../rtl/vhdl/pca9555.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/pca9555.vhdl" 118 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.009 ns + Longest register pin " "Info: + Longest register to pin delay is 7.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pca9555:pca9555_instance\|port1\[0\]~en 1 REG LC_X27_Y12_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y12_N3; Fanout = 2; REG Node = 'pca9555:pca9555_instance\|port1\[0\]~en'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pca9555:pca9555_instance|port1[0]~en } "NODE_NAME" } } { "../../rtl/vhdl/pca9555.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/pca9555.vhdl" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.935 ns) + CELL(2.074 ns) 7.009 ns led\[0\] 2 PIN PIN_50 0 " "Info: 2: + IC(4.935 ns) + CELL(2.074 ns) = 7.009 ns; Loc. = PIN_50; Fanout = 0; PIN Node = 'led\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.009 ns" { pca9555:pca9555_instance|port1[0]~en led[0] } "NODE_NAME" } } { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.074 ns ( 29.59 % ) " "Info: Total cell delay = 2.074 ns ( 29.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.935 ns ( 70.41 % ) " "Info: Total interconnect delay = 4.935 ns ( 70.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.009 ns" { pca9555:pca9555_instance|port1[0]~en led[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.009 ns" { pca9555:pca9555_instance|port1[0]~en led[0] } { 0.000ns 4.935ns } { 0.000ns 2.074ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.944 ns" { clock_50mhz pca9555:pca9555_instance|port1[0]~en } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.944 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|port1[0]~en } { 0.000ns 0.000ns 0.764ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.009 ns" { pca9555:pca9555_instance|port1[0]~en led[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.009 ns" { pca9555:pca9555_instance|port1[0]~en led[0] } { 0.000ns 4.935ns } { 0.000ns 2.074ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "pca9555:pca9555_instance\|registers\[0\]\[1\] button\[1\] clock_50mhz -3.180 ns register " "Info: th for register \"pca9555:pca9555_instance\|registers\[0\]\[1\]\" (data pin = \"button\[1\]\", clock pin = \"clock_50mhz\") is -3.180 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_50mhz destination 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clock_50mhz\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_50mhz 1 CLK PIN_28 181 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 181; CLK Node = 'clock_50mhz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock_50mhz } "NODE_NAME" } } { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns pca9555:pca9555_instance\|registers\[0\]\[1\] 2 REG LC_X1_Y17_N2 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y17_N2; Fanout = 1; REG Node = 'pca9555:pca9555_instance\|registers\[0\]\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clock_50mhz pca9555:pca9555_instance|registers[0][1] } "NODE_NAME" } } { "../../rtl/vhdl/pca9555.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/pca9555.vhdl" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clock_50mhz pca9555:pca9555_instance|registers[0][1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|registers[0][1] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "../../rtl/vhdl/pca9555.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/pca9555.vhdl" 118 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.149 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.149 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns button\[1\] 1 PIN PIN_13 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_13; Fanout = 1; PIN Node = 'button\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { button[1] } "NODE_NAME" } } { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.565 ns) + CELL(0.115 ns) 6.149 ns pca9555:pca9555_instance\|registers\[0\]\[1\] 2 REG LC_X1_Y17_N2 1 " "Info: 2: + IC(4.565 ns) + CELL(0.115 ns) = 6.149 ns; Loc. = LC_X1_Y17_N2; Fanout = 1; REG Node = 'pca9555:pca9555_instance\|registers\[0\]\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.680 ns" { button[1] pca9555:pca9555_instance|registers[0][1] } "NODE_NAME" } } { "../../rtl/vhdl/pca9555.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/pca9555.vhdl" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 25.76 % ) " "Info: Total cell delay = 1.584 ns ( 25.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.565 ns ( 74.24 % ) " "Info: Total interconnect delay = 4.565 ns ( 74.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.149 ns" { button[1] pca9555:pca9555_instance|registers[0][1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.149 ns" { button[1] button[1]~out0 pca9555:pca9555_instance|registers[0][1] } { 0.000ns 0.000ns 4.565ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clock_50mhz pca9555:pca9555_instance|registers[0][1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|registers[0][1] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.149 ns" { button[1] pca9555:pca9555_instance|registers[0][1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.149 ns" { button[1] button[1]~out0 pca9555:pca9555_instance|registers[0][1] } { 0.000ns 0.000ns 4.565ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITAN_REQUIREMENTS_MET" "" "Info: All timing requirements were met. See Report window for more details." {  } {  } 0 0 "All timing requirements were met. See Report window for more details." 0 0}