i2c_testdevice.tan.qmsg

I2C slave可以作動

{ "Info" "ITDB_FULL_SLACK_RESULT" "clock_50mhz register pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|scl_sampled\[3\] register pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|write_state.wait_scl_rising 11.424 ns " "Info: Slack time is 11.424 ns for clock \"clock_50mhz\" between source register \"pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|scl_sampled\[3\]\" and destination register \"pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|write_state.wait_scl_rising\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "116.6 MHz 8.576 ns " "Info: Fmax is 116.6 MHz (period= 8.576 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.739 ns + Largest register register " "Info: + Largest register to register requirement is 19.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock_50mhz 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock_50mhz\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock_50mhz 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock_50mhz\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_50mhz destination 2.962 ns + Shortest register " "Info: + Shortest clock path from clock \"clock_50mhz\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_50mhz 1 CLK PIN_28 181 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 181; CLK Node = 'clock_50mhz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock_50mhz } "NODE_NAME" } } { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|write_state.wait_scl_rising 2 REG LC_X24_Y14_N2 33 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X24_Y14_N2; Fanout = 33; REG Node = 'pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|write_state.wait_scl_rising'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state.wait_scl_rising } "NODE_NAME" } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 224 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state.wait_scl_rising } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state.wait_scl_rising } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_50mhz source 2.962 ns - Longest register " "Info: - Longest clock path from clock \"clock_50mhz\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_50mhz 1 CLK PIN_28 181 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 181; CLK Node = 'clock_50mhz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock_50mhz } "NODE_NAME" } } { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|scl_sampled\[3\] 2 REG LC_X25_Y15_N6 3 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X25_Y15_N6; Fanout = 3; REG Node = 'pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|scl_sampled\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[3] } "NODE_NAME" } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 150 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[3] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state.wait_scl_rising } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state.wait_scl_rising } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[3] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 150 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 224 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state.wait_scl_rising } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state.wait_scl_rising } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[3] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.315 ns - Longest register register " "Info: - Longest register to register delay is 8.315 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|scl_sampled\[3\] 1 REG LC_X25_Y15_N6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y15_N6; Fanout = 3; REG Node = 'pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|scl_sampled\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[3] } "NODE_NAME" } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 150 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.562 ns) + CELL(0.590 ns) 1.152 ns pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|Equal8~55 2 COMB LC_X25_Y15_N1 6 " "Info: 2: + IC(0.562 ns) + CELL(0.590 ns) = 1.152 ns; Loc. = LC_X25_Y15_N1; Fanout = 6; COMB Node = 'pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|Equal8~55'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.152 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[3] pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Equal8~55 } "NODE_NAME" } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.770 ns) + CELL(0.292 ns) 2.214 ns pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|Selector19~56 3 COMB LC_X25_Y15_N9 2 " "Info: 3: + IC(0.770 ns) + CELL(0.292 ns) = 2.214 ns; Loc. = LC_X25_Y15_N9; Fanout = 2; COMB Node = 'pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|Selector19~56'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.062 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Equal8~55 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Selector19~56 } "NODE_NAME" } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 225 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.793 ns) + CELL(0.292 ns) 5.299 ns pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|write_state~1306 4 COMB LC_X13_Y9_N9 2 " "Info: 4: + IC(2.793 ns) + CELL(0.292 ns) = 5.299 ns; Loc. = LC_X13_Y9_N9; Fanout = 2; COMB Node = 'pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|write_state~1306'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.085 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Selector19~56 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state~1306 } "NODE_NAME" } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 125 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.707 ns) + CELL(0.309 ns) 8.315 ns pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|write_state.wait_scl_rising 5 REG LC_X24_Y14_N2 33 " "Info: 5: + IC(2.707 ns) + CELL(0.309 ns) = 8.315 ns; Loc. = LC_X24_Y14_N2; Fanout = 33; REG Node = 'pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|write_state.wait_scl_rising'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.016 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state~1306 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state.wait_scl_rising } "NODE_NAME" } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 224 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.483 ns ( 17.84 % ) " "Info: Total cell delay = 1.483 ns ( 17.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.832 ns ( 82.16 % ) " "Info: Total interconnect delay = 6.832 ns ( 82.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.315 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[3] pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Equal8~55 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Selector19~56 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state~1306 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state.wait_scl_rising } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.315 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[3] pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Equal8~55 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Selector19~56 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state~1306 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state.wait_scl_rising } { 0.000ns 0.562ns 0.770ns 2.793ns 2.707ns } { 0.000ns 0.590ns 0.292ns 0.292ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state.wait_scl_rising } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state.wait_scl_rising } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[3] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.315 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[3] pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Equal8~55 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Selector19~56 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state~1306 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state.wait_scl_rising } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.315 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|scl_sampled[3] pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Equal8~55 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|Selector19~56 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state~1306 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|write_state.wait_scl_rising } { 0.000ns 0.562ns 0.770ns 2.793ns 2.707ns } { 0.000ns 0.590ns 0.292ns 0.292ns 0.309ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clock_50mhz register pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|input_shift\[1\] register pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|data_in\[1\] 860 ps " "Info: Minimum slack time is 860 ps for clock \"clock_50mhz\" between source register \"pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|input_shift\[1\]\" and destination register \"pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|data_in\[1\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.651 ns + Shortest register register " "Info: + Shortest register to register delay is 0.651 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|input_shift\[1\] 1 REG LC_X29_Y13_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y13_N7; Fanout = 3; REG Node = 'pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|input_shift\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|input_shift[1] } "NODE_NAME" } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.536 ns) + CELL(0.115 ns) 0.651 ns pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|data_in\[1\] 2 REG LC_X29_Y13_N9 7 " "Info: 2: + IC(0.536 ns) + CELL(0.115 ns) = 0.651 ns; Loc. = LC_X29_Y13_N9; Fanout = 7; REG Node = 'pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|data_in\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.651 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|input_shift[1] pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|data_in[1] } "NODE_NAME" } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 286 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 17.67 % ) " "Info: Total cell delay = 0.115 ns ( 17.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.536 ns ( 82.33 % ) " "Info: Total interconnect delay = 0.536 ns ( 82.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.651 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|input_shift[1] pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|data_in[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.651 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|input_shift[1] pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|data_in[1] } { 0.000ns 0.536ns } { 0.000ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock_50mhz 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock_50mhz\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock_50mhz 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock_50mhz\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_50mhz destination 2.962 ns + Longest register " "Info: + Longest clock path from clock \"clock_50mhz\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_50mhz 1 CLK PIN_28 181 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 181; CLK Node = 'clock_50mhz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock_50mhz } "NODE_NAME" } } { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|data_in\[1\] 2 REG LC_X29_Y13_N9 7 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X29_Y13_N9; Fanout = 7; REG Node = 'pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|data_in\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|data_in[1] } "NODE_NAME" } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 286 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|data_in[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|data_in[1] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_50mhz source 2.962 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_50mhz\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_50mhz 1 CLK PIN_28 181 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 181; CLK Node = 'clock_50mhz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock_50mhz } "NODE_NAME" } } { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|input_shift\[1\] 2 REG LC_X29_Y13_N7 3 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X29_Y13_N7; Fanout = 3; REG Node = 'pca9555:pca9555_instance\|i2c_slave:i2c_slave_instance\|input_shift\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|input_shift[1] } "NODE_NAME" } } { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|input_shift[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|input_shift[1] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|data_in[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|data_in[1] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|input_shift[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|input_shift[1] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 174 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "../../rtl/vhdl/i2c_slave.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/i2c_slave.vhdl" 286 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|data_in[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|data_in[1] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|input_shift[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|input_shift[1] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.651 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|input_shift[1] pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|data_in[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.651 ns" { pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|input_shift[1] pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|data_in[1] } { 0.000ns 0.536ns } { 0.000ns 0.115ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|data_in[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|data_in[1] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clock_50mhz pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|input_shift[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|i2c_slave:i2c_slave_instance|input_shift[1] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "pca9555:pca9555_instance\|selected_register_index\[1\] neg_reset clock_50mhz 9.818 ns register " "Info: tsu for register \"pca9555:pca9555_instance\|selected_register_index\[1\]\" (data pin = \"neg_reset\", clock pin = \"clock_50mhz\") is 9.818 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.723 ns + Longest pin register " "Info: + Longest pin to register delay is 12.723 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns neg_reset 1 PIN PIN_2 147 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 147; PIN Node = 'neg_reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { neg_reset } "NODE_NAME" } } { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.332 ns) + CELL(0.442 ns) 10.243 ns pca9555:pca9555_instance\|selected_register_index\[2\]~4 2 COMB LC_X29_Y13_N3 2 " "Info: 2: + IC(8.332 ns) + CELL(0.442 ns) = 10.243 ns; Loc. = LC_X29_Y13_N3; Fanout = 2; COMB Node = 'pca9555:pca9555_instance\|selected_register_index\[2\]~4'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.774 ns" { neg_reset pca9555:pca9555_instance|selected_register_index[2]~4 } "NODE_NAME" } } { "../../rtl/vhdl/pca9555.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/pca9555.vhdl" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.613 ns) + CELL(0.867 ns) 12.723 ns pca9555:pca9555_instance\|selected_register_index\[1\] 3 REG LC_X25_Y11_N8 30 " "Info: 3: + IC(1.613 ns) + CELL(0.867 ns) = 12.723 ns; Loc. = LC_X25_Y11_N8; Fanout = 30; REG Node = 'pca9555:pca9555_instance\|selected_register_index\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.480 ns" { pca9555:pca9555_instance|selected_register_index[2]~4 pca9555:pca9555_instance|selected_register_index[1] } "NODE_NAME" } } { "../../rtl/vhdl/pca9555.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/pca9555.vhdl" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.778 ns ( 21.83 % ) " "Info: Total cell delay = 2.778 ns ( 21.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.945 ns ( 78.17 % ) " "Info: Total interconnect delay = 9.945 ns ( 78.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.723 ns" { neg_reset pca9555:pca9555_instance|selected_register_index[2]~4 pca9555:pca9555_instance|selected_register_index[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.723 ns" { neg_reset neg_reset~out0 pca9555:pca9555_instance|selected_register_index[2]~4 pca9555:pca9555_instance|selected_register_index[1] } { 0.000ns 0.000ns 8.332ns 1.613ns } { 0.000ns 1.469ns 0.442ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../../rtl/vhdl/pca9555.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/pca9555.vhdl" 118 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_50mhz destination 2.942 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_50mhz\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_50mhz 1 CLK PIN_28 181 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 181; CLK Node = 'clock_50mhz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock_50mhz } "NODE_NAME" } } { "../../rtl/vhdl/t_rex_test.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/t_rex_test.vhdl" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns pca9555:pca9555_instance\|selected_register_index\[1\] 2 REG LC_X25_Y11_N8 30 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X25_Y11_N8; Fanout = 30; REG Node = 'pca9555:pca9555_instance\|selected_register_index\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.473 ns" { clock_50mhz pca9555:pca9555_instance|selected_register_index[1] } "NODE_NAME" } } { "../../rtl/vhdl/pca9555.vhdl" "" { Text "C:/data/projects/vhdl/i2c_slave/rtl/vhdl/pca9555.vhdl" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clock_50mhz pca9555:pca9555_instance|selected_register_index[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|selected_register_index[1] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.723 ns" { neg_reset pca9555:pca9555_instance|selected_register_index[2]~4 pca9555:pca9555_instance|selected_register_index[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.723 ns" { neg_reset neg_reset~out0 pca9555:pca9555_instance|selected_register_index[2]~4 pca9555:pca9555_instance|selected_register_index[1] } { 0.000ns 0.000ns 8.332ns 1.613ns } { 0.000ns 1.469ns 0.442ns 0.867ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clock_50mhz pca9555:pca9555_instance|selected_register_index[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clock_50mhz clock_50mhz~out0 pca9555:pca9555_instance|selected_register_index[1] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}