i2c_testdevice.hier_info

I2C slave可以作動

|t_rex_test
clock_50mhz => pca9555:pca9555_instance.clock
scl => pca9555:pca9555_instance.scl
sda <= pca9555:pca9555_instance.sda
led[0] <= pca9555:pca9555_instance.port1[0]
led[1] <= pca9555:pca9555_instance.port1[1]
led[2] <= pca9555:pca9555_instance.port1[2]
led[3] <= pca9555:pca9555_instance.port1[3]
led[4] <= pca9555:pca9555_instance.port1[4]
led[5] <= pca9555:pca9555_instance.port1[5]
led[6] <= pca9555:pca9555_instance.port1[6]
led[7] <= pca9555:pca9555_instance.port1[7]
button[0] => port0[0].IN1
button[1] => port0[1].IN1
button[2] => port0[2].IN1
button[3] => port0[3].IN1
dip_switch[0] => port0[4].IN1
dip_switch[1] => port0[5].IN1
dip_switch[2] => port0[6].IN1
dip_switch[3] => port0[7].IN1
neg_reset => pca9555:pca9555_instance.reset


|t_rex_test|pca9555:pca9555_instance
clock => i2c_slave:i2c_slave_instance.clock
clock => port1[0]~reg0.CLK
clock => port1[0]~en.CLK
clock => port1[1]~reg0.CLK
clock => port1[1]~en.CLK
clock => port1[2]~reg0.CLK
clock => port1[2]~en.CLK
clock => port1[3]~reg0.CLK
clock => port1[3]~en.CLK
clock => port1[4]~reg0.CLK
clock => port1[4]~en.CLK
clock => port1[5]~reg0.CLK
clock => port1[5]~en.CLK
clock => port1[6]~reg0.CLK
clock => port1[6]~en.CLK
clock => port1[7]~reg0.CLK
clock => port1[7]~en.CLK
clock => port0[0]~reg0.CLK
clock => port0[0]~en.CLK
clock => port0[1]~reg0.CLK
clock => port0[1]~en.CLK
clock => port0[2]~reg0.CLK
clock => port0[2]~en.CLK
clock => port0[3]~reg0.CLK
clock => port0[3]~en.CLK
clock => port0[4]~reg0.CLK
clock => port0[4]~en.CLK
clock => port0[5]~reg0.CLK
clock => port0[5]~en.CLK
clock => port0[6]~reg0.CLK
clock => port0[6]~en.CLK
clock => port0[7]~reg0.CLK
clock => port0[7]~en.CLK
clock => data_out[0].CLK
clock => data_out[1].CLK
clock => data_out[2].CLK
clock => data_out[3].CLK
clock => data_out[4].CLK
clock => data_out[5].CLK
clock => data_out[6].CLK
clock => data_out[7].CLK
clock => selected_register_index[0].CLK
clock => selected_register_index[1].CLK
clock => selected_register_index[2].CLK
clock => registers[7][0].CLK
clock => registers[7][1].CLK
clock => registers[7][2].CLK
clock => registers[7][3].CLK
clock => registers[7][4].CLK
clock => registers[7][5].CLK
clock => registers[7][6].CLK
clock => registers[7][7].CLK
clock => registers[6][0].CLK
clock => registers[6][1].CLK
clock => registers[6][2].CLK
clock => registers[6][3].CLK
clock => registers[6][4].CLK
clock => registers[6][5].CLK
clock => registers[6][6].CLK
clock => registers[6][7].CLK
clock => registers[5][0].CLK
clock => registers[5][1].CLK
clock => registers[5][2].CLK
clock => registers[5][3].CLK
clock => registers[5][4].CLK
clock => registers[5][5].CLK
clock => registers[5][6].CLK
clock => registers[5][7].CLK
clock => registers[4][0].CLK
clock => registers[4][1].CLK
clock => registers[4][2].CLK
clock => registers[4][3].CLK
clock => registers[4][4].CLK
clock => registers[4][5].CLK
clock => registers[4][6].CLK
clock => registers[4][7].CLK
clock => registers[3][0].CLK
clock => registers[3][1].CLK
clock => registers[3][2].CLK
clock => registers[3][3].CLK
clock => registers[3][4].CLK
clock => registers[3][5].CLK
clock => registers[3][6].CLK
clock => registers[3][7].CLK
clock => registers[2][0].CLK
clock => registers[2][1].CLK
clock => registers[2][2].CLK
clock => registers[2][3].CLK
clock => registers[2][4].CLK
clock => registers[2][5].CLK
clock => registers[2][6].CLK
clock => registers[2][7].CLK
clock => registers[1][0].CLK
clock => registers[1][1].CLK
clock => registers[1][2].CLK
clock => registers[1][3].CLK
clock => registers[1][4].CLK
clock => registers[1][5].CLK
clock => registers[1][6].CLK
clock => registers[1][7].CLK
clock => registers[0][0].CLK
clock => registers[0][1].CLK
clock => registers[0][2].CLK
clock => registers[0][3].CLK
clock => registers[0][4].CLK
clock => registers[0][5].CLK
clock => registers[0][6].CLK
clock => registers[0][7].CLK
clock => state~20.IN1
reset => i2c_slave:i2c_slave_instance.reset
reset => registers[7][0].PRESET
reset => registers[7][1].PRESET
reset => registers[7][2].PRESET
reset => registers[7][3].PRESET
reset => registers[7][4].PRESET
reset => registers[7][5].PRESET
reset => registers[7][6].PRESET
reset => registers[7][7].PRESET
reset => registers[6][0].PRESET
reset => registers[6][1].PRESET
reset => registers[6][2].PRESET
reset => registers[6][3].PRESET
reset => registers[6][4].PRESET
reset => registers[6][5].PRESET
reset => registers[6][6].PRESET
reset => registers[6][7].PRESET
reset => registers[5][0].ACLR
reset => registers[5][1].ACLR
reset => registers[5][2].ACLR
reset => registers[5][3].ACLR
reset => registers[5][4].ACLR
reset => registers[5][5].ACLR
reset => registers[5][6].ACLR
reset => registers[5][7].ACLR
reset => registers[4][0].ACLR
reset => registers[4][1].ACLR
reset => registers[4][2].ACLR
reset => registers[4][3].ACLR
reset => registers[4][4].ACLR
reset => registers[4][5].ACLR
reset => registers[4][6].ACLR
reset => registers[4][7].ACLR
reset => registers[3][0].ACLR
reset => registers[3][1].ACLR
reset => registers[3][2].ACLR
reset => registers[3][3].ACLR
reset => registers[3][4].ACLR
reset => registers[3][5].ACLR
reset => registers[3][6].ACLR
reset => registers[3][7].ACLR
reset => registers[2][0].ACLR
reset => registers[2][1].ACLR
reset => registers[2][2].ACLR
reset => registers[2][3].ACLR
reset => registers[2][4].ACLR
reset => registers[2][5].ACLR
reset => registers[2][6].ACLR
reset => registers[2][7].ACLR
reset => registers[1][0].ACLR
reset => registers[1][1].ACLR
reset => registers[1][2].ACLR
reset => registers[1][3].ACLR
reset => registers[1][4].ACLR
reset => registers[1][5].ACLR
reset => registers[1][6].ACLR
reset => registers[1][7].ACLR
reset => registers[0][0].ACLR
reset => registers[0][1].ACLR
reset => registers[0][2].ACLR
reset => registers[0][3].ACLR
reset => registers[0][4].ACLR
reset => registers[0][5].ACLR
reset => registers[0][6].ACLR
reset => registers[0][7].ACLR
reset => port1[6]~reg0.ENA
reset => port1[5]~en.ENA
reset => port1[5]~reg0.ENA
reset => port1[4]~en.ENA
reset => port1[4]~reg0.ENA
reset => port1[3]~en.ENA
reset => port1[3]~reg0.ENA
reset => port1[2]~en.ENA
reset => port1[2]~reg0.ENA
reset => port1[1]~en.ENA
reset => port1[1]~reg0.ENA
reset => port1[0]~en.ENA
reset => port1[0]~reg0.ENA
reset => port1[6]~en.ENA
reset => port1[7]~reg0.ENA
reset => port1[7]~en.ENA
reset => port0[0]~reg0.ENA
reset => port0[0]~en.ENA
reset => port0[1]~reg0.ENA
reset => port0[1]~en.ENA
reset => port0[2]~reg0.ENA
reset => port0[2]~en.ENA
reset => port0[3]~reg0.ENA
reset => port0[3]~en.ENA
reset => port0[4]~reg0.ENA
reset => port0[4]~en.ENA
reset => port0[5]~reg0.ENA
reset => port0[5]~en.ENA
reset => port0[6]~reg0.ENA
reset => port0[6]~en.ENA
reset => port0[7]~reg0.ENA
reset => port0[7]~en.ENA
reset => selected_register_index[0].ENA
reset => state~21.IN1
scl => i2c_slave:i2c_slave_instance.scl
sda <= i2c_slave:i2c_slave_instance.sda
port0[0] <= comb~8
port0[1] <= comb~9
port0[2] <= comb~10
port0[3] <= comb~11
port0[4] <= comb~12
port0[5] <= comb~13
port0[6] <= comb~14
port0[7] <= comb~15
port1[0] <= comb~5
port1[1] <= comb~4
port1[2] <= comb~3
port1[3] <= comb~2
port1[4] <= comb~1
port1[5] <= comb~0
port1[6] <= comb~6
port1[7] <= comb~7


|t_rex_test|pca9555:pca9555_instance|i2c_slave:i2c_slave_instance
clock => data_in[0]~reg0.CLK
clock => data_in[1]~reg0.CLK
clock => data_in[2]~reg0.CLK
clock => data_in[3]~reg0.CLK
clock => data_in[4]~reg0.CLK
clock => data_in[5]~reg0.CLK
clock => data_in[6]~reg0.CLK
clock => data_in[7]~reg0.CLK
clock => read_mode_received.CLK
clock => write_ack.CLK
clock => read_ack.CLK
clock => write_byte.CLK
clock => read_byte.CLK
clock => data_in_valid~reg0.CLK
clock => data_out_requested~reg0.CLK
clock => transfer_started~reg0.CLK
clock => write_timeout_counter[0].CLK
clock => write_timeout_counter[1].CLK
clock => write_timeout_counter[2].CLK
clock => write_timeout_counter[3].CLK
clock => write_timeout_counter[4].CLK
clock => write_timeout_counter[5].CLK
clock => write_timeout_counter[6].CLK
clock => write_timeout_counter[7].CLK
clock => write_timeout_counter[8].CLK
clock => write_timeout_counter[9].CLK
clock => write_timeout_counter[10].CLK
clock => write_timeout_counter[11].CLK
clock => write_timeout_counter[12].CLK
clock => write_timeout_counter[13].CLK
clock => write_timeout_counter[14].CLK
clock => write_timeout_counter[15].CLK
clock => output_shift_count[0].CLK
clock => output_shift_count[1].CLK
clock => output_shift_count[2].CLK
clock => sda_out.CLK
clock => output_shift[0].CLK
clock => output_shift[1].CLK
clock => output_shift[2].CLK
clock => output_shift[3].CLK
clock => output_shift[4].CLK
clock => output_shift[5].CLK
clock => output_shift[6].CLK
clock => output_shift[7].CLK
clock => input_shift_count[0].CLK
clock => input_shift_count[1].CLK
clock => input_shift_count[2].CLK
clock => input_shift[0].CLK
clock => input_shift[1].CLK
clock => input_shift[2].CLK
clock => input_shift[3].CLK
clock => input_shift[4].CLK
clock => input_shift[5].CLK
clock => input_shift[6].CLK
clock => input_shift[7].CLK
clock => sample_cycles_counter[0].CLK
clock => sample_cycles_counter[1].CLK
clock => sample_cycles_counter[2].CLK
clock => sample_cycles_counter[3].CLK
clock => scl_sampled[0].CLK
clock => scl_sampled[1].CLK
clock => scl_sampled[2].CLK
clock => scl_sampled[3].CLK
clock => sda_sampled[0].CLK
clock => sda_sampled[1].CLK
clock => sda_sampled[2].CLK
clock => sda_sampled[3].CLK
clock => control_state~48.IN1
clock => write_state~37.IN1
clock => read_state~24.IN1
reset => output_shift[0].ACLR
reset => output_shift[1].ACLR
reset => output_shift[2].ACLR
reset => output_shift[3].ACLR
reset => output_shift[4].ACLR
reset => output_shift[5].ACLR
reset => output_shift[6].ACLR
reset => output_shift[7].ACLR
reset => input_shift[0].ACLR
reset => input_shift[1].ACLR
reset => input_shift[2].ACLR
reset => input_shift[3].ACLR
reset => input_shift[4].ACLR
reset => input_shift[5].ACLR
reset => input_shift[6].ACLR
reset => input_shift[7].ACLR
reset => sample_cycles_counter[0].ACLR
reset => sample_cycles_counter[1].ACLR
reset => sample_cycles_counter[2].ACLR
reset => sample_cycles_counter[3].ACLR
reset => scl_sampled[0].PRESET
reset => scl_sampled[1].PRESET
reset => scl_sampled[2].PRESET
reset => scl_sampled[3].PRESET
reset => sda_sampled[0].PRESET
reset => sda_sampled[1].PRESET
reset => sda_sampled[2].PRESET
reset => sda_sampled[3].PRESET
reset => read_mode_received.ENA
reset => write_ack.ENA
reset => read_ack.ENA
reset => write_byte.ENA
reset => read_byte.ENA
reset => data_in_valid~reg0.ENA
reset => data_out_requested~reg0.ENA
reset => transfer_started~reg0.ENA
reset => write_timeout_counter[0].ENA
reset => write_timeout_counter[1].ENA
reset => write_timeout_counter[2].ENA
reset => write_timeout_counter[3].ENA
reset => write_timeout_counter[4].ENA
reset => write_timeout_counter[5].ENA
reset => write_timeout_counter[6].ENA
reset => write_timeout_counter[7].ENA
reset => write_timeout_counter[8].ENA
reset => write_timeout_counter[9].ENA
reset => write_timeout_counter[10].ENA
reset => write_timeout_counter[11].ENA
reset => write_timeout_counter[12].ENA
reset => write_timeout_counter[13].ENA
reset => write_timeout_counter[14].ENA
reset => write_timeout_counter[15].ENA
reset => output_shift_count[0].ENA
reset => output_shift_count[1].ENA
reset => output_shift_count[2].ENA
reset => sda_out.ENA
reset => input_shift_count[0].ENA
reset => input_shift_count[1].ENA
reset => input_shift_count[2].ENA
reset => control_state~49.IN1
reset => write_state~38.IN1
reset => read_state~25.IN1
data_out[0] => output_shift~15.DATAB
data_out[1] => output_shift~14.DATAB
data_out[2] => output_shift~13.DATAB
data_out[3] => output_shift~12.DATAB
data_out[4] => output_shift~11.DATAB
data_out[5] => output_shift~10.DATAB
data_out[6] => output_shift~9.DATAB
data_out[7] => output_shift~8.DATAB
data_in[0] <= data_in[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[1] <= data_in[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[2] <= data_in[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[3] <= data_in[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[4] <= data_in[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[5] <= data_in[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[6] <= data_in[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[7] <= data_in[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
read_mode <= read_mode_received.DB_MAX_OUTPUT_PORT_TYPE
start_detected <= start_detected_delayed~2.DB_MAX_OUTPUT_PORT_TYPE
stop_detected <= stop_detected_delayed~1.DB_MAX_OUTPUT_PORT_TYPE
transfer_started <= transfer_started~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out_requested <= data_out_requested~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in_valid <= data_in_valid~reg0.DB_MAX_OUTPUT_PORT_TYPE
sda <= comb~0
scl => scl_sampled[0].DATAIN