📄 drivers.lst
字号:
0088 97 TAX
0089 af01 AIX #1
008b 8b PSHH
008c 86 PULA
008d 47 ASRA
008e 56 RORX
008f 9ee701 STA 1,SP
0092 9ee605 LDA 5,SP
0095 87 PSHA
0096 4f CLRA
0097 87 PSHA
0098 9f TXA
0099 95 TSX
009a ee02 LDX 2,X
009c cd0000 JSR _ICMP
009f 92a1 BGT L42 ;abs = 0042
325: }
326: DeAssertCE; /* Disables MC13192 SPI */
00a1 1400 BSET 2,_PTED
327: restore_MC13192_interrupts(); /* Restore MC13192 interrupt status */
00a3 cd0000 JSR restore_MC13192_interrupts
328: }
00a6 a707 AIS #7
00a8 81 RTS
329:
330: /**************************************************************
331: * Function: read a block of data from RX packet RAM (whichever is selected)
332: * Parameters: *length returned length of the block of data in bytes
333: * *contents pointer to the data block storage
334: **************************************************************/
335: int drv_read_rx_ram(rx_packet_t *rx_pkt)
336: {
Function: drv_read_rx_ram
Source : D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\Sources\drivers.c
Options : -Cs08 -DAXM_0308 -Env"GENPATH=*D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac;D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\target\include;*C:\Program Files\Metrowerks\CW08 V3.1" -Env"LIBPATH=*C:\Program Files\Metrowerks\CW08 V3.1" -Env"OBJPATH=D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\bin" -Env"TEXTPATH=D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\bin" -Lasm=%n.lst -Ms -ObjN="D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\smac_Data\GB60_(EVB_-_rev_A-B-C)\ObjectCode\drivers.c.o" -WmsgSd1106 -WmsgSd1420 -WmsgSd1801 -WmsgSd2705
0000 89 PSHX
0001 8b PSHH
0002 a7f9 AIS #-7
337: __uint8__ i, ibyte, temp_value; /* i, ibyte are counters. temp_value is used to flush the SPI1D register during read */
338: __uint8__ status=0; /* holder for the return value */
0004 95 TSX
0005 6f06 CLR 6,X
339: __uint16__ rx_length;
340: rx_length = drv_read_spi_1(RX_PKT_LEN); /* Read the RX packet length register contents */
0007 a62d LDA #45
0009 cd0000 JSR drv_read_spi_1
000c 9eff02 STHX 2,SP
341: rx_length &= 0x007F; /* Mask out all but the RX packet length */
000f 95 TSX
0010 e602 LDA 2,X
0012 a47f AND #127
0014 e702 STA 2,X
0016 6f01 CLR 1,X
342: /* MC13192 reports length with 2 CRC bytes, remove them. */
343: /* ShortPacket is also checked in RX_ISR */
344: if (rx_length >= 3)
0018 9efe02 LDHX 2,SP
001b 650003 CPHX #3
001e 2509 BCS L29 ;abs = 0029
345: {
346: rx_pkt->dataLength = rx_length - 2;
0020 a002 SUB #2
0022 9efe08 LDHX 8,SP
0025 e701 STA 1,X
347: }
0027 2005 BRA L2E ;abs = 002e
0029 L29:
348: else
349: {
350: rx_pkt->dataLength = 0;
0029 9efe08 LDHX 8,SP
002c 6f01 CLR 1,X
002e L2E:
351: }
352: if ((rx_pkt->dataLength >= 1) && (rx_pkt->dataLength <= rx_pkt->maxDataLength)) /* If <3, the packet is garbage */
002e 9efe08 LDHX 8,SP
0031 6d01 TST 1,X
0033 2603 BNE L38 ;abs = 0038
0035 cc00da JMP LDA ;abs = 00da
0038 L38:
0038 f6 LDA ,X
0039 e101 CMP 1,X
003b 2403 BCC L40 ;abs = 0040
003d cc00da JMP LDA ;abs = 00da
0040 L40:
353: {
354: temp_value = SPI1S; /* Clear status register (possible SPRF, SPTEF) */
0040 b600 LDA _SPI1S
355: temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
0042 b600 LDA _SPI1D
356: disable_MC13192_interrupts(); /* Necessary to prevent double SPI access */
0044 cd0000 JSR disable_MC13192_interrupts
357: AssertCE; /* Enables MC13192 SPI */
0047 1500 BCLR 2,_PTED
358: SPI1D = RX_PKT | 0x80; /* SPI RX ram data register */
0049 6e8100 MOV #-127,_SPI1D
359: WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set.*/
004c cd0000 JSR WaitSPI_transfer_done
360: temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
004f b600 LDA _SPI1D
0051 cd00ed JSR LED ;abs = 00ed
361: SPI1D = temp_value; /* Dummy write. Receive register of SPI will contain MSB garbage for first read */
362: WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set.*/
363: temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
0054 b600 LDA _SPI1D
0056 cd00ed JSR LED ;abs = 00ed
364: SPI1D = temp_value; /* Dummy write. Receive register of SPI will contain LSB garbage for first read */
365: WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set.*/
366: temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
0059 b600 LDA _SPI1D
005b 95 TSX
005c e704 STA 4,X
367: ibyte = 0; /* Byte counter for *contents */
005e 6f03 CLR 3,X
368: for (i=0; i<((rx_length-1)>>1); i++) /* Word loop. Round up. Deduct CRC. */
0060 6f05 CLR 5,X
0062 204f BRA LB3 ;abs = 00b3
0064 L64:
369: {
370: SPI1D = temp_value; /* Dummy write. Receive register of SPI will contain MSB */
0064 95 TSX
0065 e604 LDA 4,X
0067 cd00ed JSR LED ;abs = 00ed
371: WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set. Get MSB */
372: if ((ibyte+3)==rx_length) /* For a trailing garbage byte, just read and discard */
006a 95 TSX
006b e603 LDA 3,X
006d 8c CLRH
006e 97 TAX
006f af03 AIX #3
0071 9ef302 CPHX 2,SP
0074 2607 BNE L7D ;abs = 007d
373: {
374: temp_value = SPI1D; /* Discard */
0076 b600 LDA _SPI1D
0078 95 TSX
0079 e704 STA 4,X
375: }
007b 2017 BRA L94 ;abs = 0094
007d L7D:
376: else
377: {
378: rx_pkt->data[ibyte+1] = SPI1D; /* Read MSB */
007d 8c CLRH
007e 97 TAX
007f af01 AIX #1
0081 9f TXA
0082 8b PSHH
0083 9efe09 LDHX 9,SP
0086 eb03 ADD 3,X
0088 87 PSHA
0089 9ee602 LDA 2,SP
008c e902 ADC 2,X
008e 87 PSHA
008f 8a PULH
0090 88 PULX
0091 5e00 MOV _SPI1D,X+
0093 8a PULH
0094 L94:
379: }
380: SPI1D = temp_value; /* Dummy write. Receive register of SPI will contain LSB */
0094 95 TSX
0095 e604 LDA 4,X
0097 ad54 BSR LED ;abs = 00ed
381: WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set. Get LSB */
382: rx_pkt->data[ibyte] = SPI1D; /* Read LSB */
0099 9efe08 LDHX 8,SP
009c 9ee604 LDA 4,SP
009f eb03 ADD 3,X
00a1 87 PSHA
00a2 4f CLRA
00a3 e902 ADC 2,X
00a5 87 PSHA
00a6 8a PULH
00a7 88 PULX
00a8 5e00 MOV _SPI1D,X+
383: ibyte=ibyte+2; /* Increment byte counter */
00aa 95 TSX
00ab e603 LDA 3,X
00ad ab02 ADD #2
00af e703 STA 3,X
00b1 6c05 INC 5,X
00b3 LB3:
00b3 9efe02 LDHX 2,SP
00b6 afff AIX #-1
00b8 8b PSHH
00b9 86 PULA
00ba 44 LSRA
00bb 56 RORX
00bc 9ee701 STA 1,SP
00bf 9ee606 LDA 6,SP
00c2 87 PSHA
00c3 4f CLRA
00c4 87 PSHA
00c5 9f TXA
00c6 95 TSX
00c7 ee02 LDX 2,X
00c9 cd0000 JSR _ICMP
00cc 2296 BHI L64 ;abs = 0064
384: }
385: DeAssertCE; /* Disables MC13192 SPI */
00ce 1400 BSET 2,_PTED
386: rx_pkt->status = SUCCESS;
00d0 9efe08 LDHX 8,SP
00d3 a677 LDA #119
00d5 e704 STA 4,X
387: restore_MC13192_interrupts(); /* Restore MC13192 interrupt status */
00d7 cd0000 JSR restore_MC13192_interrupts
00da LDA:
388: }
389: /* Check to see if a larger packet than desired is received. */
390: if (rx_pkt->dataLength > rx_pkt->maxDataLength)
00da 9efe08 LDHX 8,SP
00dd f6 LDA ,X
00de e101 CMP 1,X
00e0 2404 BCC LE6 ;abs = 00e6
391: rx_pkt->status = OVERFLOW;
00e2 a601 LDA #1
00e4 e704 STA 4,X
00e6 LE6:
392: return status;
00e6 95 TSX
00e7 ee06 LDX 6,X
00e9 8c CLRH
393: }
00ea a709 AIS #9
00ec 81 RTS
00ed LED:
00ed b700 STA _SPI1D
00ef cc0000 JMP WaitSPI_transfer_done
394:
395:
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