📄 drivers.lst
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00b9 410240 CBEQA #2,LFC ;abs = 00fc
00bc 41803d CBEQA #-128,LFC ;abs = 00fc
00bf 41013a CBEQA #1,LFC ;abs = 00fc
00c2 2015 BRA LD9 ;abs = 00d9
00c4 LC4:
127: {
128: status_content = (drv_read_spi_1(MODE_ADDR) & 0xFF7F); /* Read the MC13192 trx register. Timer trigger off. */
129: drv_write_spi_1(MODE_ADDR, status_content); /* Re-write the trx register. */
130: AssertRTXEN(); /* Re-start the sequence. */
131: }
132: else
133: {
134: rtx_mode = IDLE_MODE;
135: }
136: return;
137: }
138: if ((rtx_mode == IDLE_MODE) || ((status_content & CCA_IRQ_MASK) != 0) || ((status_content & TX_IRQ_MASK) != 0))
00c4 c60000 LDA rtx_mode
00c7 270d BEQ LD6 ;abs = 00d6
00c9 95 TSX
00ca e601 LDA 1,X
00cc a520 BIT #32
00ce 2606 BNE LD6 ;abs = 00d6
00d0 e601 LDA 1,X
00d2 a540 BIT #64
00d4 2709 BEQ LDF ;abs = 00df
00d6 LD6:
139: {
140: /* If in idle mode already or if CCA or TX is done, just return. */
141: DeAssertRTXEN(); /* Forces the MC13192 to idle. */
00d6 cd0000 JSR DeAssertRTXEN
00d9 LD9:
142: rtx_mode = IDLE_MODE;
00d9 4f CLRA
00da LDA:
00da c70000 STA rtx_mode
00dd LDD:
00dd 204b BRA L12A ;abs = 012a
00df LDF:
143: return;
144: }
145: /* If rx is done */
146: if ((status_content & RX_IRQ_MASK) != 0)
00df e601 LDA 1,X
00e1 2a47 BPL L12A ;abs = 012a
147: {
148: DeAssertRTXEN(); /* Forces the MC13192 to idle. */
00e3 cd0000 JSR DeAssertRTXEN
149: if ((status_content & CRC_VALID_MASK) == 0)
00e6 95 TSX
00e7 e601 LDA 1,X
00e9 a501 BIT #1
00eb 270f BEQ LFC ;abs = 00fc
150: {
151: /* If an invalid CRC, restart receiver. */
152: status_content = (drv_read_spi_1(MODE_ADDR) & 0xFF7F); /* Read the MC13192 trx register. Timer trigger off. */
153: drv_write_spi_1(MODE_ADDR, status_content); /* Update the trx register. */
154: AssertRTXEN(); /* Forces the MC13192 to enter the receive mode. */
155: return;
156: }
157: else
158: {
159: dataLength = (__uint8__) (drv_read_spi_1(RX_PKT_LEN) & 0x7F); /* Read received packet length register and mask off length bits */
00ed a62d LDA #45
00ef cd0000 JSR drv_read_spi_1
00f2 9f TXA
00f3 a47f AND #127
00f5 95 TSX
00f6 e702 STA 2,X
160: if (dataLength < 3) /* Rx_pkt_length is bad when 0, 1 or 2. */
00f8 a103 CMP #3
00fa 2419 BCC L115 ;abs = 0115
00fc LFC:
161: {
162: status_content = (drv_read_spi_1(MODE_ADDR) & 0xFF7F); /* Read the MC13192 trx register. Timer trigger off. */
00fc a606 LDA #6
00fe cd0000 JSR drv_read_spi_1
0101 9f TXA
0102 a47f AND #127
0104 97 TAX
0105 9eff01 STHX 1,SP
163: drv_write_spi_1(MODE_ADDR, status_content); /* Update the trx register. */
0108 a606 LDA #6
010a 9efe01 LDHX 1,SP
010d cd0000 JSR drv_write_spi_1
164: AssertRTXEN(); /* Forces the MC13192 to enter the receive mode. */
0110 cd0000 JSR AssertRTXEN
0113 2015 BRA L12A ;abs = 012a
0115 L115:
165: return;
166: }
167: /* A valid packet has been received. */
168: rtx_mode = IDLE_MODE; /* set the rtx_state to idle */
0115 5f CLRX
0116 cf0000 STX rtx_mode
0119 ad13 BSR L12E ;abs = 012e
169: drv_write_spi_1(T1_HI_ADDR, 0x8000); /* Disables TC1 and clears the IRQ. */
170: drv_write_spi_1(T1_LO_ADDR, 0x0000);
171: drv_rx_packet->dataLength = dataLength;
011b 95 TSX
011c e602 LDA 2,X
011e 320000 LDHX drv_rx_packet
0121 e701 STA 1,X
172: drv_rx_packet->status = SUCCESS;
0123 a677 LDA #119
0125 e704 STA 4,X
0127 L127:
173: pd_data_indication(); /* Notify PHY that there is data available. */
0127 cd0000 JSR pd_data_indication
012a L12A:
174: return;
175: }
176: }
177: }
012a a705 AIS #5
012c 8a PULH
012d 80 RTI
012e L12E:
012e a61b LDA #27
0130 458000 LDHX #-32768
0133 cd0000 JSR drv_write_spi_1
0136 a61c LDA #28
0138 5f CLRX
0139 8c CLRH
013a cc0000 JMP drv_write_spi_1
178:
179: /**************************************************************
180: * Function: Wake the MC13192 from Hibernate/Doze mode
181: * Parameters: none
182: * Return:
183: **************************************************************/
184: void Wake_MC13192 (void)
185: {
Function: Wake_MC13192
Source : D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\Sources\drivers.c
Options : -Cs08 -DAXM_0308 -Env"GENPATH=*D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac;D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\target\include;*C:\Program Files\Metrowerks\CW08 V3.1" -Env"LIBPATH=*C:\Program Files\Metrowerks\CW08 V3.1" -Env"OBJPATH=D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\bin" -Env"TEXTPATH=D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\bin" -Lasm=%n.lst -Ms -ObjN="D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\smac_Data\GB60_(EVB_-_rev_A-B-C)\ObjectCode\drivers.c.o" -WmsgSd1106 -WmsgSd1420 -WmsgSd1801 -WmsgSd2705
186: MC13192_ATTN = 0; /* Assert ATTN */
0000 1b00 BCLR 5,_PTDD
187: MC13192_ATTN = 1; /* Deassert ATTN */
0002 1a00 BSET 5,_PTDD
188: }
0004 81 RTS
189:
190: /**************************************************************
191: * Function: Deassert the MC13192 RTXEN pin (forces IC to idle)
192: * Parameters: none
193: * Return:
194: **************************************************************/
195: void DeAssertRTXEN(void)
196: {
Function: DeAssertRTXEN
Source : D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\Sources\drivers.c
Options : -Cs08 -DAXM_0308 -Env"GENPATH=*D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac;D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\target\include;*C:\Program Files\Metrowerks\CW08 V3.1" -Env"LIBPATH=*C:\Program Files\Metrowerks\CW08 V3.1" -Env"OBJPATH=D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\bin" -Env"TEXTPATH=D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\bin" -Lasm=%n.lst -Ms -ObjN="D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\smac_Data\GB60_(EVB_-_rev_A-B-C)\ObjectCode\drivers.c.o" -WmsgSd1106 -WmsgSd1420 -WmsgSd1801 -WmsgSd2705
197: MC13192_RTXEN = 0; /* Deassert RTXEN */
0000 1d00 BCLR 6,_PTDD
198: }
0002 81 RTS
199:
200: /**************************************************************
201: * Function: Assert the MC13192 RTXEN pin (initiates programmed cycle)
202: * Parameters: none
203: * Return:
204: **************************************************************/
205: void AssertRTXEN(void)
206: {
Function: AssertRTXEN
Source : D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\Sources\drivers.c
Options : -Cs08 -DAXM_0308 -Env"GENPATH=*D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac;D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\target\include;*C:\Program Files\Metrowerks\CW08 V3.1" -Env"LIBPATH=*C:\Program Files\Metrowerks\CW08 V3.1" -Env"OBJPATH=D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\bin" -Env"TEXTPATH=D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\bin" -Lasm=%n.lst -Ms -ObjN="D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\smac_Data\GB60_(EVB_-_rev_A-B-C)\ObjectCode\drivers.c.o" -WmsgSd1106 -WmsgSd1420 -WmsgSd1801 -WmsgSd2705
207: MC13192_RTXEN = 1; /* Assert RTXEN */
0000 1c00 BSET 6,_PTDD
208: }
0002 81 RTS
209:
210: /**************************************************************
211: * Function: write 1 word to SPI
212: * Parameters: SPI address, the word
213: * Return:
214: **************************************************************/
215: void drv_write_spi_1(__uint8__ addr, __uint16__ content)
216: {
Function: drv_write_spi_1
Source : D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\Sources\drivers.c
Options : -Cs08 -DAXM_0308 -Env"GENPATH=*D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac;D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\target\include;*C:\Program Files\Metrowerks\CW08 V3.1" -Env"LIBPATH=*C:\Program Files\Metrowerks\CW08 V3.1" -Env"OBJPATH=D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\bin" -Env"TEXTPATH=D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\bin" -Lasm=%n.lst -Ms -ObjN="D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\smac_Data\GB60_(EVB_-_rev_A-B-C)\ObjectCode\drivers.c.o" -WmsgSd1106 -WmsgSd1420 -WmsgSd1801 -WmsgSd2705
0000 87 PSHA
0001 89 PSHX
0002 8b PSHH
217: __uint8__ temp_value; /* Used to flush the SPI1D register during read */
218: temp_value = SPI1S; /* Clear status register (possible SPRF, SPTEF) */
0003 b600 LDA _SPI1S
219: temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
0005 b600 LDA _SPI1D
220: disable_MC13192_interrupts(); /* Necessary to prevent double SPI access */
0007 cd0000 JSR disable_MC13192_interrupts
221: AssertCE; /* Enables MC13192 SPI */
000a 1500 BCLR 2,_PTED
222: SPI1D = addr & 0x3F; /* Mask address, 6bit addr. Set write bit (i.e. 0). */
000c 95 TSX
000d e602 LDA 2,X
000f a43f AND #63
0011 ad11 BSR L24 ;abs = 0024
223: WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set. Now write content MSB */
224: temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
225: SPI1D = content >> 8; /* Write MSB */
0013 95 TSX
0014 f6 LDA ,X
0015 ad0d BSR L24 ;abs = 0024
226: WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set. Now write content LSB */
227: temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
228: SPI1D = content & 0x00FF; /* Write LSB */
0017 95 TSX
0018 e601 LDA 1,X
001a ad08 BSR L24 ;abs = 0024
229: WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set. Now read last of garbage */
230: temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
231: DeAssertCE; /* Disables MC13192 SPI */
001c 1400 BSET 2,_PTED
232: restore_MC13192_interrupts(); /* Restore MC13192 interrupt status */
001e cd0000 JSR restore_MC13192_interrupts
233: }
0021 a703 AIS #3
0023 81 RTS
0024 L24:
0024 b700 STA _SPI1D
0026 cd0000 JSR WaitSPI_transfer_done
0029 b600 LDA _SPI1D
002b 81 RTS
234:
235: /**************************************************************
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