📄 drivers.lst
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ANSI-C/cC++ Compiler for HC08 V-5.0.19 (beta 0) Build 4210, Jul 29 2004
1: /**************************************************************
2: * This is the SMAC C source driver file for the HC(S)08 MCU
3: * and MC13192 transceiver.
4: * The driver controls all interfaces to/from the MC13192 by the
5: * SPI, selected interrupt source and MCU GPIO's assigned to
6: * other MC13192 pins.
7: * The SMAC driver is the lowest layer of C code.
8: * Actual hardware interconnects from the MCU to the MC13192 are
9: * defined in the MC13192_hw_config.h header file.
10: **************************************************************/
11:
12:
13: /**************************************************************
14: * Includes
15: **************************************************************/
16: #include "device_header.h"
17: #include "pub_def.h"
18: #include "drivers.h"
19: #include "MC13192_regs.h"
20: #include "MC13192_hw_config.h"
21: #include "mcu_hw_config.h"
22: #include "simple_phy.h"
23:
24: /**************************************************************
25: * Defines
26: **************************************************************/
27: #define AssertCE MC13192_CE = 0 /* Asserts the MC13192 CE pin */
28: #define DeAssertCE MC13192_CE = 1 /* Deasserts the MC13192 CE pin */
29: #define SPIClkInvert SPIC1 |= 0x04; /*Set CPHA bit of SPCR (clk polarity) */
30: #define SPIClkNormal SPIC1 &= 0xFB; /*clr CPHA bit of SPCR (clk polarity) */
31:
32: /**************************************************************
33: * Globals
34: **************************************************************/
35: rx_packet_t *drv_rx_packet;
36: cca_measurement_t drv_cca_reading;
37: __uint8__ irq_value = 0;
38: extern byte rtx_mode;
39:
40: /**************************************************************
41: * Interrupt: MC13192 initiated interrupt handler
42: * Parameters: none
43: * Return: The interrupt will RTI unless valid data is recvd.
44: * In this case a pd_data_indication function call-back
45: * will be executed first, followed by a RTI
46: **************************************************************/
47: interrupt void irq_isr(void)
48: {
Function: irq_isr
Source : D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\Sources\drivers.c
Options : -Cs08 -DAXM_0308 -Env"GENPATH=*D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac;D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\target\include;*C:\Program Files\Metrowerks\CW08 V3.1" -Env"LIBPATH=*C:\Program Files\Metrowerks\CW08 V3.1" -Env"OBJPATH=D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\bin" -Env"TEXTPATH=D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\bin" -Lasm=%n.lst -Ms -ObjN="D:\Profiles\flr005\My Documents\Bluetooth Exchange Folder\smac 4_0\CW_IDE_3p1\smac\smac_Data\GB60_(EVB_-_rev_A-B-C)\ObjectCode\drivers.c.o" -WmsgSd1106 -WmsgSd1420 -WmsgSd1801 -WmsgSd2705
0000 8b PSHH
0001 a7fb AIS #-5
49: /* The vector is defined in vectortable.c */
50: volatile __uint16__ status_content, reg; /* Result of the status register read. */
51: __uint8__ dataLength = 0; /* Data length for the RX packet */
0003 95 TSX
0004 6f02 CLR 2,X
52: CLEAR_IRQ_FLAG; /* Acknowledge the interrupt. MC13192 IRQ pin still low. */
0006 1400 BSET 2,_IRQSC
53: status_content = drv_read_spi_1(STATUS_ADDR); /* Read the MC13192 status register. */
0008 a624 LDA #36
000a cd0000 JSR drv_read_spi_1
000d 9eff01 STHX 1,SP
54: /* Replace this with C code, if possible!!!!!!!!!!!!*/
55: /* Test for IRQ glitch or possible fast double IRQ. */
56: asm
57: {
58: BIH irq_high
0010 2f25 BIH L37 ;abs = 0037
59: }
60: /* IRQ is low. Re-read status. */
61: CLEAR_IRQ_FLAG; /* Acknowledge the interrupt. MC13192 IRQ pin still low. */
0012 1400 BSET 2,_IRQSC
62: reg = drv_read_spi_1(STATUS_ADDR); /* Read the MC13192 status register. */
0014 a624 LDA #36
0016 cd0000 JSR drv_read_spi_1
0019 9eff04 STHX 4,SP
63: status_content = status_content | reg; /* Actual status is the OR of both. */
001c 9efe04 LDHX 4,SP
001f 89 PSHX
0020 8b PSHH
0021 9efe03 LDHX 3,SP
0024 9f TXA
0025 8b PSHH
0026 95 TSX
0027 ea02 ORA 2,X
0029 e702 STA 2,X
002b 86 PULA
002c ea01 ORA 1,X
002e 87 PSHA
002f ee02 LDX 2,X
0031 8a PULH
0032 9eff03 STHX 3,SP
0035 a702 AIS #2
0037 L37:
64: asm
65: {
66: irq_high:
67: }
68: status_content &= TX_IRQ_MASK | RX_IRQ_MASK | ATTN_IRQ_MASK | CRC_VALID_MASK | TIMER1_IRQ_MASK | CCA_IRQ_MASK | LO_LOCK_IRQ_MASK;
0037 9efe01 LDHX 1,SP
003a 9f TXA
003b a4e1 AND #-31
003d 87 PSHA
003e 8b PSHH
003f 86 PULA
0040 a485 AND #-123
0042 87 PSHA
0043 8a PULH
0044 88 PULX
0045 9eff01 STHX 1,SP
69: if (rtx_mode != RX_MODE_WTO)
0048 c60000 LDA rtx_mode
004b 418009 CBEQA #-128,L57 ;abs = 0057
70: {
71: /* If timeout not being used, mask out timer. */
72: status_content &= ~(TIMER1_IRQ_MASK);
004e 95 TSX
004f e601 LDA 1,X
0051 e701 STA 1,X
0053 f6 LDA ,X
0054 a4fe AND #-2
0056 f7 STA ,X
0057 L57:
73: }
74: if ((status_content & ~(CRC_VALID_MASK)) == 0)
0057 95 TSX
0058 e601 LDA 1,X
005a a4fe AND #-2
005c 87 PSHA
005d f6 LDA ,X
005e 87 PSHA
005f 8a PULH
0060 88 PULX
0061 650000 CPHX #0
0064 2777 BEQ LDD ;abs = 00dd
75: {
76: /* If no status bits are set just return. */
77: return;
78: }
79: /* DOZE Complete Interrupt */
80: if ((status_content & DOZE_IRQ_MASK) != 0)
81: {
82: /* Not implemented!!!!!!!!!!!!!! */
83: }
84: /* ATTN IRQ Handler*/
85: if ((status_content & ATTN_IRQ_MASK) != 0)
0066 a504 BIT #4
0068 2726 BEQ L90 ;abs = 0090
86: {
87: /* If attn interrupt, set the rtx_state mirror. */
88: /* For MC13192 V2.x devices, read the reset indication in R25/7 first. */
89: /* If a reset is indicated, call back to a reset handler. */
90: status_content = drv_read_spi_1(RESIND_ADDR); /* Read the MC13192 reset indicator register. */
006a a625 LDA #37
006c cd0000 JSR drv_read_spi_1
006f 9eff01 STHX 1,SP
91: status_content &= RESET_BIT_MASK;
0072 95 TSX
0073 ee01 LDX 1,X
0075 9f TXA
0076 a480 AND #-128
0078 8c CLRH
0079 97 TAX
007a 9eff01 STHX 1,SP
92: if (status_content == 0) /* Reset */
007d 9efe01 LDHX 1,SP
0080 260a BNE L8C ;abs = 008c
93: {
94: rtx_mode = MC13192_RESET_MODE; /* Set the rtx_state mirror to idle with attn. */
0082 a687 LDA #-121
0084 c70000 STA rtx_mode
95: PLME_MC13192_reset_indication();
0087 cd0000 JSR PLME_MC13192_reset_indication
008a L8A:
96: return;
008a 2051 BRA LDD ;abs = 00dd
008c L8C:
97: }
98: else
99: {
100: rtx_mode = IDLE_MODE_ATTN; /* Set the rtx_state mirror to idle with attn. */
008c a684 LDA #-124
101: return;
008e 204a BRA LDA ;abs = 00da
0090 L90:
102: }
103: }
104: /* TIMER1 IRQ Handler (Used for receiver timeout notification) */
105: if ((status_content & TIMER1_IRQ_MASK) != 0)
0090 a501 BIT #1
0092 271a BEQ LAE ;abs = 00ae
106: {
107: /* If a timeout (and timeout enabled) is done, update the mode mirror state. */
108: if (rtx_mode == RX_MODE_WTO)
0094 c60000 LDA rtx_mode
0097 a180 CMP #-128
0099 2613 BNE LAE ;abs = 00ae
009b cd012e JSR L12E ;abs = 012e
109: {
110: /* Clear Timer1 if in RX_MODE_WTO */
111: drv_write_spi_1(T1_HI_ADDR, 0x8000); /* Disables TC1 and clears the IRQ. */
112: drv_write_spi_1(T1_LO_ADDR, 0x0000);
113: drv_rx_packet->status = TIMEOUT;
009e a685 LDA #-123
00a0 320000 LDHX drv_rx_packet
00a3 e704 STA 4,X
114: DeAssertRTXEN(); /* Forces the MC13192 to idle. */
00a5 cd0000 JSR DeAssertRTXEN
115: rtx_mode = IDLE_MODE;
00a8 4f CLRA
00a9 c70000 STA rtx_mode
116: /* TIMEOUT notification */
117: pd_data_indication();
118: return;
00ac 2079 BRA L127 ;abs = 0127
00ae LAE:
119: }
120: }
121: /* LO LOCK IRQ - Occurs when MC13192 loses LOCK */
122: /* For receive cycles, re-enable. For transmit/CCA, abort. */
123: if ((status_content & LO_LOCK_IRQ_MASK) != 0)
00ae 8b PSHH
00af 86 PULA
00b0 4d TSTA
00b1 2a11 BPL LC4 ;abs = 00c4
124: {
125: DeAssertRTXEN(); /* Forces the MC13192 to idle. */
00b3 cd0000 JSR DeAssertRTXEN
126: if ((rtx_mode == RX_MODE) || (rtx_mode == RX_MODE_WTO) || (rtx_mode == CCA_MODE)) /* Unlock from receive cycles */
00b6 c60000 LDA rtx_mode
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