📄 drivers.c
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/**************************************************************
* Function: Assert the MC13192 RTXEN pin (initiates programmed cycle)
* Parameters: none
* Return:
**************************************************************/
void AssertRTXEN(void)
{
MC13192_RTXEN = 1; /* Assert RTXEN */
}
/**************************************************************
* Function: write 1 word to SPI
* Parameters: SPI address, the word
* Return:
**************************************************************/
void drv_write_spi_1(__uint8__ addr, __uint16__ content)
{
__uint8__ temp_value; /* Used to flush the SPI1D register during read */
temp_value = SPI1S; /* Clear status register (possible SPRF, SPTEF) */
temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
disable_MC13192_interrupts(); /* Necessary to prevent double SPI access */
AssertCE; /* Enables MC13192 SPI */
SPI1D = addr & 0x3F; /* Mask address, 6bit addr. Set write bit (i.e. 0). */
WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set. Now write content MSB */
temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
SPI1D = content >> 8; /* Write MSB */
WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set. Now write content LSB */
temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
SPI1D = content & 0x00FF; /* Write LSB */
WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set. Now read last of garbage */
temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
DeAssertCE; /* Disables MC13192 SPI */
restore_MC13192_interrupts(); /* Restore MC13192 interrupt status */
}
/**************************************************************
* Function: read 1 word from SPI
* Parameters: SPI address
* Return: a word, w. w[0] is the MSB, w[1] is the LSB
**************************************************************/
__uint16__ drv_read_spi_1(__uint8__ addr)
{
__uint16__ w; /* w[0] is MSB, w[1] is LSB */
__uint8__ temp_value; /* Used to flush the SPI1D register during read */
temp_value = SPI1S; /* Clear status register (possible SPRF, SPTEF) */
temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
disable_MC13192_interrupts(); /* Necessary to prevent double SPI access */
AssertCE; /* Enables MC13192 SPI */
SPI1D = (addr & 0x3f) | 0x80; /* Mask address, 6bit addr, Set read bit. */
WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set */
temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
SPI1D = addr; /* Dummy write. Receive register of SPI will contain MSB */
WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set. Get MSB */
((__uint8__*)&w)[0] = SPI1D; /* MSB */
SPI1D = addr; /* Dummy write. Waiting until after reading received data insures no overrun */
WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set. Get LSB */
((__uint8__*)&w)[1] = SPI1D; /* LSB */
DeAssertCE; /* Disables MC13192 SPI */
restore_MC13192_interrupts(); /* Restore MC13192 interrupt status */
return w;
}
/**************************************************************
* Parameters: None
* Purpose: Waits until the SPI1D has been transferred and received
**************************************************************/
void WaitSPI_transfer_done(void)
{
while (!(SPI1S_SPRF))
{
}
}
/**************************************************************
* Function: disable MC13192 interrupts
* Parameters: none
* Return:
**************************************************************/
void disable_MC13192_interrupts(void)
{
irq_value = MC13192_IRQ_SOURCE; /* Save the context of the MC13192_INT_REG (global) */
MC13192_IRQ_SOURCE = irq_value & ~(0x06); /* Disable the MC13192 interrupt source */
}
/**************************************************************
* Function: restore MC13192 interrupts to previous condition
* Parameters: none
* Return:
**************************************************************/
void restore_MC13192_interrupts(void)
{
MC13192_IRQ_SOURCE = irq_value; /* Restore the context of the IRQ register from global */
}
/**************************************************************
* Function: write a block of data to TX packet RAM (whichever is selected)
* Parameters: length length of the block of data in bytes
* *contents pointer to the data block
**************************************************************/
void drv_write_tx_ram(tx_packet_t *tx_pkt)
{
__uint8__ i, ibyte, temp_value; /* i, ibyte are counters. temp_value is used to flush the SPI1D register during read */
__uint16__ reg; /* TX packet length register value */
reg = drv_read_spi_1(TX_PKT_LEN); /* Read the TX packet length register contents */
reg = (0xFF80 & reg) | (tx_pkt->dataLength + 2); /* Mask out old length setting and update. Add 2 for CRC */
drv_write_spi_1(TX_PKT_LEN, reg); /* Update the TX packet length field */
temp_value = SPI1S; /* Clear status register (possible SPRF, SPTEF) */
temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
disable_MC13192_interrupts(); /* Necessary to prevent double SPI access */
AssertCE; /* Enables MC13192 SPI */
SPI1D = TX_PKT; /* SPI TX ram data register */
WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set. Now write content MSB */
temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
ibyte = 0; /* Byte counter for *contents */
for (i=0; i<((tx_pkt->dataLength+1) >> 1); i++) /* Word loop. Round up. */
{
SPI1D = tx_pkt->data[ibyte + 1]; /* Write MSB */
WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set. Now write content LSB */
temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
SPI1D = tx_pkt->data[ibyte]; /* Write LSB */
ibyte=ibyte+2; /* Increment byte counter */
WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set.*/
temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
}
DeAssertCE; /* Disables MC13192 SPI */
restore_MC13192_interrupts(); /* Restore MC13192 interrupt status */
}
/**************************************************************
* Function: read a block of data from RX packet RAM (whichever is selected)
* Parameters: *length returned length of the block of data in bytes
* *contents pointer to the data block storage
**************************************************************/
int drv_read_rx_ram(rx_packet_t *rx_pkt)
{
__uint8__ i, ibyte, temp_value; /* i, ibyte are counters. temp_value is used to flush the SPI1D register during read */
__uint8__ status=0; /* holder for the return value */
__uint16__ rx_length;
rx_length = drv_read_spi_1(RX_PKT_LEN); /* Read the RX packet length register contents */
rx_length &= 0x007F; /* Mask out all but the RX packet length */
/* MC13192 reports length with 2 CRC bytes, remove them. */
/* ShortPacket is also checked in RX_ISR */
if (rx_length >= 3)
{
rx_pkt->dataLength = rx_length - 2;
}
else
{
rx_pkt->dataLength = 0;
}
if ((rx_pkt->dataLength >= 1) && (rx_pkt->dataLength <= rx_pkt->maxDataLength)) /* If <3, the packet is garbage */
{
temp_value = SPI1S; /* Clear status register (possible SPRF, SPTEF) */
temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
disable_MC13192_interrupts(); /* Necessary to prevent double SPI access */
AssertCE; /* Enables MC13192 SPI */
SPI1D = RX_PKT | 0x80; /* SPI RX ram data register */
WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set.*/
temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
SPI1D = temp_value; /* Dummy write. Receive register of SPI will contain MSB garbage for first read */
WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set.*/
temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
SPI1D = temp_value; /* Dummy write. Receive register of SPI will contain LSB garbage for first read */
WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set.*/
temp_value = SPI1D; /* Clear receive data register. SPI entirely ready for read or write */
ibyte = 0; /* Byte counter for *contents */
for (i=0; i<((rx_length-1)>>1); i++) /* Word loop. Round up. Deduct CRC. */
{
SPI1D = temp_value; /* Dummy write. Receive register of SPI will contain MSB */
WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set. Get MSB */
if ((ibyte+3)==rx_length) /* For a trailing garbage byte, just read and discard */
{
temp_value = SPI1D; /* Discard */
}
else
{
rx_pkt->data[ibyte+1] = SPI1D; /* Read MSB */
}
SPI1D = temp_value; /* Dummy write. Receive register of SPI will contain LSB */
WaitSPI_transfer_done(); /* For this bit to be set, SPTED MUST be set. Get LSB */
rx_pkt->data[ibyte] = SPI1D; /* Read LSB */
ibyte=ibyte+2; /* Increment byte counter */
}
DeAssertCE; /* Disables MC13192 SPI */
rx_pkt->status = SUCCESS;
restore_MC13192_interrupts(); /* Restore MC13192 interrupt status */
}
/* Check to see if a larger packet than desired is received. */
if (rx_pkt->dataLength > rx_pkt->maxDataLength)
rx_pkt->status = OVERFLOW;
return status;
}
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