📄 svm.mdl
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Points [0, 75]
DstBlock "饱和判断2"
DstPort 2
}
}
Line {
SrcBlock "Mux"
SrcPort 1
DstBlock "Fcn"
DstPort 1
}
Line {
SrcBlock "Mux1"
SrcPort 1
DstBlock "Fcn1"
DstPort 1
}
Line {
SrcBlock "Fcn1"
SrcPort 1
Points [15, 0; 0, -145]
DstBlock "饱和判断2"
DstPort 1
}
Line {
SrcBlock "Fcn"
SrcPort 1
Points [25, 0; 0, 70]
DstBlock "饱和判断1"
DstPort 1
}
Line {
SrcBlock "N"
SrcPort 1
Points [215, 0; 60, 0]
Branch {
DstBlock "T11"
DstPort 1
}
Branch {
Points [0, 210]
DstBlock "T21"
DstPort 1
}
}
Line {
SrcBlock "饱和判断1"
SrcPort 1
DstBlock "T1"
DstPort 1
}
Line {
SrcBlock "饱和判断2"
SrcPort 1
DstBlock "T2"
DstPort 1
}
Line {
SrcBlock "T"
SrcPort 1
Points [390, 0]
Branch {
Points [40, 0]
DstBlock "Mux1"
DstPort 3
}
Branch {
Points [0, -340]
DstBlock "Mux"
DstPort 3
}
}
}
}
Block {
BlockType SubSystem
Name "Taon,Tbon,Tcon"
Ports [3, 3]
Position [575, 46, 635, 144]
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Taon,Tbon,Tcon"
Location [2, 82, 1014, 721]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "T1"
Position [25, 133, 55, 147]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "T2"
Position [20, 263, 50, 277]
Port "2"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "T"
Position [20, 313, 50, 327]
Port "3"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Gain
Name "Gain"
Position [395, 255, 425, 285]
Gain "1/4"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain1"
Position [395, 125, 425, 155]
Gain "0.5"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain2"
Position [390, 30, 420, 60]
Gain "0.5"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Sum
Name "Sum"
Ports [3, 1]
Position [330, 246, 355, 294]
ShowName off
Inputs "--+"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Sum
Name "Sum1"
Ports [2, 1]
Position [530, 133, 555, 162]
ShowName off
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Sum
Name "Sum2"
Ports [2, 1]
Position [585, 38, 610, 67]
ShowName off
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Outport
Name "Taon"
Position [695, 263, 725, 277]
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Tbon"
Position [690, 143, 720, 157]
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Tcon"
Position [690, 48, 720, 62]
Port "3"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "T"
SrcPort 1
Points [120, 0; 0, -35]
DstBlock "Sum"
DstPort 3
}
Line {
SrcBlock "T2"
SrcPort 1
Points [160, 0]
Branch {
Points [0, -225]
DstBlock "Gain2"
DstPort 1
}
Branch {
DstBlock "Sum"
DstPort 2
}
}
Line {
SrcBlock "T1"
SrcPort 1
Points [0, 0; 250, 0]
Branch {
DstBlock "Gain1"
DstPort 1
}
Branch {
Points [0, 115]
DstBlock "Sum"
DstPort 1
}
}
Line {
SrcBlock "Sum"
SrcPort 1
DstBlock "Gain"
DstPort 1
}
Line {
SrcBlock "Gain"
SrcPort 1
Points [70, 0]
Branch {
DstBlock "Taon"
DstPort 1
}
Branch {
Points [0, -115]
DstBlock "Sum1"
DstPort 2
}
}
Line {
SrcBlock "Gain1"
SrcPort 1
DstBlock "Sum1"
DstPort 1
}
Line {
SrcBlock "Sum1"
SrcPort 1
Points [0, 0; 10, 0]
Branch {
DstBlock "Tbon"
DstPort 1
}
Branch {
DstBlock "Sum2"
DstPort 2
}
}
Line {
SrcBlock "Gain2"
SrcPort 1
DstBlock "Sum2"
DstPort 1
}
Line {
SrcBlock "Sum2"
SrcPort 1
DstBlock "Tcon"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "Time"
Ports [4, 3]
Position [260, 41, 330, 144]
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Time"
Location [205, 238, 790, 464]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "Ubeta"
Position [25, 48, 55, 62]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "Ualfa"
Position [25, 88, 55, 102]
Port "2"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "T"
Position [25, 128, 55, 142]
Port "3"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "Udc"
Position [25, 168, 55, 182]
Port "4"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Fcn
Name "Fcn"
Position [355, 25, 415, 55]
Expr "1.732*u(1)*u(3)/u(4)"
}
Block {
BlockType Fcn
Name "Fcn1"
Position [355, 100, 415, 130]
Expr "0.5*(1.732*u(1)+3*u(2))*u(3)/u(4)"
}
Block {
BlockType Fcn
Name "Fcn2"
Position [355, 165, 415, 195]
Expr "0.5*(1.732*u(1)-3*u(2))*u(3)/u(4)"
}
Block {
BlockType Mux
Name "Mux"
Ports [4, 1]
Position [210, 31, 240, 199]
ShowName off
}
Block {
BlockType Outport
Name "X"
Position [520, 33, 550, 47]
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Y"
Position [520, 108, 550, 122]
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Z"
Position [520, 173, 550, 187]
Port "3"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Ubeta"
SrcPort 1
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "Ualfa"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "T"
SrcPort 1
DstBlock "Mux"
DstPort 3
}
Line {
SrcBlock "Udc"
SrcPort 1
DstBlock "Mux"
DstPort 4
}
Line {
SrcBlock "Mux"
SrcPort 1
Points [0, 0; 45, 0]
Branch {
Points [0, -75]
DstBlock "Fcn"
DstPort 1
}
Branch {
DstBlock "Fcn1"
DstPort 1
}
Branch {
Points [0, 65]
DstBlock "Fcn2"
DstPort 1
}
}
Line {
SrcBlock "Fcn"
SrcPort 1
DstBlock "X"
DstPort 1
}
Line {
SrcBlock "Fcn1"
SrcPort 1
DstBlock "Y"
DstPort 1
}
Line {
SrcBlock "Fcn2"
SrcPort 1
DstBlock "Z"
DstPort 1
}
Annotation {
Position [224, 84]
}
}
}
Block {
BlockType SubSystem
Name "d,q/alfa,beta"
Ports [2, 2]
Position [95, 25, 145, 100]
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "d,q/alfa,beta"
Location [2, 82, 1014, 721]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "Ud"
Position [165, 168, 195, 182]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "Uq"
Position [165, 198, 195, 212]
Port "2"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Constant
Name "Constant"
Position [165, 235, 195, 265]
Value "0"
}
Block {
BlockType Reference
Name "Discrete\nVirtual PLL"
Ports [0, 3]
Position [195, 283, 265, 327]
SourceBlock "powerlib_extras/Discrete \nControl Bloc"
"ks/Discrete\nVirtual PLL"
SourceType "Discrete Virtual PLL"
ShowPortLabels "on"
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