hammingcode_synthesis.nlf

几个VHDL的源码小程序

Release 8.2.03i - netgen I.34
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -ar Structure -tm hammingcode -w -dir
netgen/synthesis -ofmt vhdl -sim hammingcode.ngc hammingcode_synthesis.vhd  

Reading design 'hammingcode.ngc' ...
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist
'E:\simulink\xilinx_work\hamming_code\netgen\synthesis\hammingcode_synthesis.vhd
' ...
INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIM
   simulation primitives and has to be used with UNISIM library for correct
   compilation and simulation. 
Number of warnings: 0
Number of info messages: 1
Total memory usage is 58168 kilobytes