hammingcode_synthesis.vhd

几个VHDL的源码小程序

    );
  error_add_proc_code_count_Madd_add0000_Mxor_Result_1_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => error_add_proc_code_count(0),
      I1 => error_add_proc_code_count(1),
      O => error_add_proc_code_count_add0000(1)
    );
  decode_proc_mux00051 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => decode_proc_dout_rd_3,
      I1 => decode_proc_state_reg_FFd2_13,
      I2 => decode_proc_state_reg_FFd1_12,
      O => decode_proc_mux0005
    );
  error_add_proc_code_count_Madd_add0000_Mxor_Result_2_Result1 : LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => error_add_proc_code_count(2),
      I1 => error_add_proc_code_count(1),
      I2 => error_add_proc_code_count(0),
      O => error_add_proc_code_count_add0000(2)
    );
  decode_proc_state_reg_FFd2_In1 : LUT4
    generic map(
      INIT => X"2722"
    )
    port map (
      I0 => decode_proc_state_reg_FFd2_13,
      I1 => decode_proc_state_reg_FFd1_12,
      I2 => decode_proc_data_nd_dly_11,
      I3 => error_add_proc_dout_rd_5,
      O => decode_proc_state_reg_FFd2_In
    );
  error_add_proc_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => error_add_proc_data_nd_dly_10,
      I1 => encode_proc_dout_rd_4,
      O => error_add_proc_and0000
    );
  encode_proc_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => encode_proc_data_nd_dly_9,
      I1 => data_nd_IBUF_2,
      O => encode_proc_and0000
    );
  clk_BUFGP : BUFGP
    port map (
      I => clk,
      O => clk_BUFGP_0
    );
  aclr_IBUF : IBUF
    port map (
      I => aclr,
      O => aclr_IBUF_1
    );
  data_nd_IBUF : IBUF
    port map (
      I => data_nd,
      O => data_nd_IBUF_2
    );
  data_in_2_IBUF : IBUF
    port map (
      I => data_in(2),
      O => data_in_2_IBUF_6
    );
  data_in_1_IBUF : IBUF
    port map (
      I => data_in(1),
      O => data_in_1_IBUF_7
    );
  data_in_0_IBUF : IBUF
    port map (
      I => data_in(0),
      O => data_in_0_IBUF_8
    );
  dout_rd_OBUF : OBUF
    port map (
      I => decode_proc_dout_rd_3,
      O => dout_rd
    );
  error_out_3_OBUF : OBUF
    port map (
      I => decode_proc_error_out(3),
      O => error_out(3)
    );
  error_out_2_OBUF : OBUF
    port map (
      I => decode_proc_error_out(2),
      O => error_out(2)
    );
  error_out_1_OBUF : OBUF
    port map (
      I => decode_proc_error_out(1),
      O => error_out(1)
    );
  error_out_0_OBUF : OBUF
    port map (
      I => decode_proc_error_out(0),
      O => error_out(0)
    );
  decode_out_3_OBUF : OBUF
    port map (
      I => decode_proc_error_out(3),
      O => decode_out(3)
    );
  decode_out_2_OBUF : OBUF
    port map (
      I => decode_proc_error_out(2),
      O => decode_out(2)
    );
  decode_out_1_OBUF : OBUF
    port map (
      I => decode_proc_error_out(1),
      O => decode_out(1)
    );
  decode_out_0_OBUF : OBUF
    port map (
      I => decode_proc_dout(0),
      O => decode_out(0)
    );
  error_add_proc_dout_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => error_add_proc_dout(6),
      O => error_add_proc_dout_6_rt_15
    );
  decode_proc_mux0004_2_5 : LUT4
    generic map(
      INIT => X"FF9A"
    )
    port map (
      I0 => decode_proc_bit_count(0),
      I1 => decode_proc_bit_count(2),
      I2 => decode_proc_bit_count(1),
      I3 => decode_proc_state_reg_FFd1_12,
      O => decode_proc_mux0004_2_map58
    );
  decode_proc_mux0004_1_5 : LUT4
    generic map(
      INIT => X"FF95"
    )
    port map (
      I0 => decode_proc_bit_count(0),
      I1 => decode_proc_bit_count(1),
      I2 => decode_proc_bit_count(2),
      I3 => decode_proc_state_reg_FFd1_12,
      O => decode_proc_mux0004_1_map73
    );
  decode_proc_mux0004_2_48 : LUT4
    generic map(
      INIT => X"BA10"
    )
    port map (
      I0 => decode_proc_syn(0),
      I1 => N100,
      I2 => decode_proc_mux0000,
      I3 => decode_proc_mux0004_2_map65,
      O => decode_proc_mux0004(2)
    );
  decode_proc_mux0004_1_48 : LUT4
    generic map(
      INIT => X"BA10"
    )
    port map (
      I0 => decode_proc_syn(1),
      I1 => N102,
      I2 => decode_proc_mux0000,
      I3 => decode_proc_mux0004_1_map80,
      O => decode_proc_mux0004(1)
    );
  decode_proc_mux0004_2_25 : MUXF5
    port map (
      I0 => N108,
      I1 => N109,
      S => decode_proc_state_reg_FFd2_13,
      O => decode_proc_mux0004_2_map65
    );
  decode_proc_mux0004_2_25_F : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => error_add_proc_dout_rd_5,
      I1 => decode_proc_data_nd_dly_11,
      O => N108
    );
  decode_proc_mux0004_2_25_G : LUT4
    generic map(
      INIT => X"CEDF"
    )
    port map (
      I0 => decode_proc_bit_count(2),
      I1 => decode_proc_mux0004_2_map58,
      I2 => decode_proc_bit_count_1_f5_14,
      I3 => decode_proc_bit_count_1_f51,
      O => N109
    );
  decode_proc_mux0004_1_25 : MUXF5
    port map (
      I0 => N110,
      I1 => N111,
      S => decode_proc_state_reg_FFd2_13,
      O => decode_proc_mux0004_1_map80
    );
  decode_proc_mux0004_1_25_F : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => error_add_proc_dout_rd_5,
      I1 => decode_proc_data_nd_dly_11,
      O => N110
    );
  decode_proc_mux0004_1_25_G : LUT4
    generic map(
      INIT => X"CEDF"
    )
    port map (
      I0 => decode_proc_bit_count(2),
      I1 => decode_proc_mux0004_1_map73,
      I2 => decode_proc_bit_count_1_f5_14,
      I3 => decode_proc_bit_count_1_f51,
      O => N111
    );
  error_add_proc_Mxor_xor0000_Result_5_1 : LUT4
    generic map(
      INIT => X"C9CC"
    )
    port map (
      I0 => error_add_proc_code_count(1),
      I1 => encode_proc_dout(5),
      I2 => error_add_proc_code_count(2),
      I3 => error_add_proc_code_count(0),
      O => error_add_proc_xor0000(5)
    );
  error_add_proc_Mxor_xor0000_Result_3_1 : LUT4
    generic map(
      INIT => X"9CCC"
    )
    port map (
      I0 => error_add_proc_code_count(2),
      I1 => encode_proc_dout(3),
      I2 => error_add_proc_code_count(1),
      I3 => error_add_proc_code_count(0),
      O => error_add_proc_xor0000(3)
    );
  error_add_proc_Mxor_xor0000_Result_2_1 : LUT4
    generic map(
      INIT => X"C9CC"
    )
    port map (
      I0 => error_add_proc_code_count(0),
      I1 => encode_proc_dout(2),
      I2 => error_add_proc_code_count(1),
      I3 => error_add_proc_code_count(2),
      O => error_add_proc_xor0000(2)
    );
  error_add_proc_Mxor_xor0000_Result_4_1 : LUT4
    generic map(
      INIT => X"C9CC"
    )
    port map (
      I0 => error_add_proc_code_count(0),
      I1 => encode_proc_dout(4),
      I2 => error_add_proc_code_count(2),
      I3 => error_add_proc_code_count(1),
      O => error_add_proc_xor0000(4)
    );
  error_add_proc_Mxor_xor0000_Result_0_1 : LUT4
    generic map(
      INIT => X"9CCC"
    )
    port map (
      I0 => error_add_proc_code_count(0),
      I1 => encode_proc_dout(0),
      I2 => error_add_proc_code_count(1),
      I3 => error_add_proc_code_count(2),
      O => error_add_proc_xor0000(0)
    );
  error_add_proc_Mxor_xor0000_Result_1_1 : LUT4
    generic map(
      INIT => X"9CCC"
    )
    port map (
      I0 => error_add_proc_code_count(1),
      I1 => encode_proc_dout(1),
      I2 => error_add_proc_code_count(0),
      I3 => error_add_proc_code_count(2),
      O => error_add_proc_xor0000(1)
    );
  decode_proc_Mxor_xor0000_Result_0_1 : LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => error_add_proc_dout(3),
      I1 => decode_proc_syn(0),
      I2 => decode_proc_syn(1),
      O => decode_proc_xor0000(0)
    );
  decode_proc_mux0003_1_Q : MUXF5
    port map (
      I0 => N112,
      I1 => N113,
      S => decode_proc_state_reg_FFd2_13,
      O => decode_proc_mux0003(1)
    );
  decode_proc_mux0003_1_F : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => decode_proc_bit_count(1),
      I1 => error_add_proc_dout_rd_5,
      I2 => decode_proc_data_nd_dly_11,
      O => N112
    );
  decode_proc_mux0003_1_G : LUT4
    generic map(
      INIT => X"AEA6"
    )
    port map (
      I0 => decode_proc_bit_count(1),
      I1 => decode_proc_bit_count(0),
      I2 => decode_proc_state_reg_FFd1_12,
      I3 => decode_proc_bit_count(2),
      O => N113
    );
  decode_proc_mux0003_2_Q : MUXF5
    port map (
      I0 => N114,
      I1 => N115,
      S => decode_proc_state_reg_FFd2_13,
      O => decode_proc_mux0003(2)
    );
  decode_proc_mux0003_2_F : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => decode_proc_bit_count(0),
      I1 => error_add_proc_dout_rd_5,
      I2 => decode_proc_data_nd_dly_11,
      O => N114
    );
  decode_proc_mux0003_2_G : LUT4
    generic map(
      INIT => X"B999"
    )
    port map (
      I0 => decode_proc_bit_count(0),
      I1 => decode_proc_state_reg_FFd1_12,
      I2 => decode_proc_bit_count(2),
      I3 => decode_proc_bit_count(1),
      O => N115
    );
  decode_proc_mux0003_0_Q : MUXF5
    port map (
      I0 => N116,
      I1 => N117,
      S => decode_proc_state_reg_FFd2_13,
      O => decode_proc_mux0003(0)
    );
  decode_proc_mux0003_0_F : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => decode_proc_bit_count(2),
      I1 => error_add_proc_dout_rd_5,
      I2 => decode_proc_data_nd_dly_11,
      O => N116
    );
  decode_proc_mux0003_0_G : LUT4
    generic map(
      INIT => X"AAEA"
    )
    port map (
      I0 => decode_proc_bit_count(2),
      I1 => decode_proc_bit_count(0),
      I2 => decode_proc_bit_count(1),
      I3 => decode_proc_state_reg_FFd1_12,
      O => N117
    );
  error_add_proc_code_count_Madd_add0000_not00001_INV_0 : INV
    port map (
      I => error_add_proc_code_count(0),
      O => error_add_proc_code_count_add0000(0)
    );
  XST_VCC : VCC
    port map (
      P => N118
    );
  XST_GND : GND
    port map (
      G => N119
    );
  decode_proc_state_reg_FFd1_In11 : LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      I0 => decode_proc_bit_count(2),
      I1 => decode_proc_bit_count(0),
      I2 => decode_proc_bit_count(1),
      I3 => decode_proc_state_reg_FFd1_12,
      O => N120
    );
  decode_proc_state_reg_FFd1_In1_f5 : MUXF5
    port map (
      I0 => N119,
      I1 => N120,
      S => decode_proc_state_reg_FFd2_13,
      O => decode_proc_state_reg_FFd1_In
    );
  decode_proc_mux0004_1_31_SW01 : LUT4
    generic map(
      INIT => X"FF9A"
    )
    port map (
      I0 => decode_proc_bit_count(0),
      I1 => decode_proc_bit_count(2),
      I2 => decode_proc_bit_count(1),
      I3 => decode_proc_state_reg_FFd1_12,
      O => N121
    );
  decode_proc_mux0004_1_31_SW0_f5 : MUXF5
    port map (
      I0 => N118,
      I1 => N121,
      S => decode_proc_state_reg_FFd2_13,
      O => N100
    );
  decode_proc_mux0004_1_31_SW11 : LUT4
    generic map(
      INIT => X"FF95"
    )
    port map (
      I0 => decode_proc_bit_count(0),
      I1 => decode_proc_bit_count(1),
      I2 => decode_proc_bit_count(2),
      I3 => decode_proc_state_reg_FFd1_12,
      O => N122
    );
  decode_proc_mux0004_1_31_SW1_f5 : MUXF5
    port map (
      I0 => N118,
      I1 => N122,
      S => decode_proc_state_reg_FFd2_13,
      O => N102
    );

end Structure;