hammingcode_synthesis.vhd

几个VHDL的源码小程序

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: I.34
--  \   \         Application: netgen
--  /   /         Filename: hammingcode_synthesis.vhd
-- /___/   /\     Timestamp: Fri Oct 31 08:48:58 2008
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -ar Structure -tm hammingcode -w -dir netgen/synthesis -ofmt vhdl -sim hammingcode.ngc hammingcode_synthesis.vhd 
-- Device	: xa3s50-4-vqg100
-- Input file	: hammingcode.ngc
-- Output file	: E:\simulink\xilinx_work\hamming_code\netgen\synthesis\hammingcode_synthesis.vhd
-- # of Entities	: 1
-- Design Name	: hammingcode
-- Xilinx	: D:\Xilinx
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity hammingcode is
  port (
    clk : in STD_LOGIC := 'X'; 
    aclr : in STD_LOGIC := 'X'; 
    data_nd : in STD_LOGIC := 'X'; 
    dout_rd : out STD_LOGIC; 
    data_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    error_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    decode_out : out STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
end hammingcode;

architecture Structure of hammingcode is
  signal clk_BUFGP_0 : STD_LOGIC; 
  signal aclr_IBUF_1 : STD_LOGIC; 
  signal data_nd_IBUF_2 : STD_LOGIC; 
  signal decode_proc_dout_rd_3 : STD_LOGIC; 
  signal encode_proc_dout_rd_4 : STD_LOGIC; 
  signal error_add_proc_dout_rd_5 : STD_LOGIC; 
  signal data_in_2_IBUF_6 : STD_LOGIC; 
  signal data_in_1_IBUF_7 : STD_LOGIC; 
  signal data_in_0_IBUF_8 : STD_LOGIC; 
  signal encode_proc_data_nd_dly_9 : STD_LOGIC; 
  signal encode_proc_and0000 : STD_LOGIC; 
  signal error_add_proc_data_nd_dly_10 : STD_LOGIC; 
  signal error_add_proc_and0000 : STD_LOGIC; 
  signal N10 : STD_LOGIC; 
  signal N11 : STD_LOGIC; 
  signal N12 : STD_LOGIC; 
  signal N13 : STD_LOGIC; 
  signal decode_proc_data_nd_dly_11 : STD_LOGIC; 
  signal decode_proc_state_reg_FFd1_12 : STD_LOGIC; 
  signal decode_proc_mux0000 : STD_LOGIC; 
  signal decode_proc_mux0005 : STD_LOGIC; 
  signal decode_proc_state_reg_FFd2_13 : STD_LOGIC; 
  signal decode_proc_state_reg_FFd1_In : STD_LOGIC; 
  signal decode_proc_state_reg_FFd2_In : STD_LOGIC; 
  signal decode_proc_N21 : STD_LOGIC; 
  signal decode_proc_bit_count_1_f5_14 : STD_LOGIC; 
  signal decode_proc_N31 : STD_LOGIC; 
  signal decode_proc_N41 : STD_LOGIC; 
  signal decode_proc_bit_count_1_f51 : STD_LOGIC; 
  signal decode_proc_mux0004_2_map58 : STD_LOGIC; 
  signal decode_proc_mux0004_2_map65 : STD_LOGIC; 
  signal decode_proc_mux0004_1_map73 : STD_LOGIC; 
  signal decode_proc_mux0004_1_map80 : STD_LOGIC; 
  signal error_add_proc_dout_6_rt_15 : STD_LOGIC; 
  signal N100 : STD_LOGIC; 
  signal N102 : STD_LOGIC; 
  signal N108 : STD_LOGIC; 
  signal N109 : STD_LOGIC; 
  signal N110 : STD_LOGIC; 
  signal N111 : STD_LOGIC; 
  signal N112 : STD_LOGIC; 
  signal N113 : STD_LOGIC; 
  signal N114 : STD_LOGIC; 
  signal N115 : STD_LOGIC; 
  signal N116 : STD_LOGIC; 
  signal N117 : STD_LOGIC; 
  signal N118 : STD_LOGIC; 
  signal N119 : STD_LOGIC; 
  signal N120 : STD_LOGIC; 
  signal N121 : STD_LOGIC; 
  signal N122 : STD_LOGIC; 
  signal decode_proc_error_out : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal decode_proc_dout : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal encode_proc_dout : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal error_add_proc_dout : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal error_add_proc_code_count : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal error_add_proc_xor0000 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal error_add_proc_code_count_add0000 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal decode_proc_bit_count : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal decode_proc_mux0003 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal decode_proc_syn : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal decode_proc_mux0004 : STD_LOGIC_VECTOR ( 2 downto 1 ); 
  signal decode_proc_xor0000 : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  encode_proc_data_nd_dly : FDC
    port map (
      D => data_nd_IBUF_2,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => encode_proc_data_nd_dly_9
    );
  encode_proc_dout_rd : FDC
    port map (
      D => encode_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => encode_proc_dout_rd_4
    );
  encode_proc_dout_0 : FDCE
    port map (
      D => N11,
      CE => encode_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => encode_proc_dout(0)
    );
  encode_proc_dout_1 : FDCE
    port map (
      D => N12,
      CE => encode_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => encode_proc_dout(1)
    );
  encode_proc_dout_2 : FDCE
    port map (
      D => N13,
      CE => encode_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => encode_proc_dout(2)
    );
  encode_proc_dout_3 : FDCE
    port map (
      D => data_in_0_IBUF_8,
      CE => encode_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => encode_proc_dout(3)
    );
  encode_proc_dout_4 : FDCE
    port map (
      D => data_in_1_IBUF_7,
      CE => encode_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => encode_proc_dout(4)
    );
  encode_proc_dout_5 : FDCE
    port map (
      D => data_in_2_IBUF_6,
      CE => encode_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => encode_proc_dout(5)
    );
  error_add_proc_data_nd_dly : FDC
    port map (
      D => encode_proc_dout_rd_4,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => error_add_proc_data_nd_dly_10
    );
  error_add_proc_dout_rd : FDC
    port map (
      D => error_add_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => error_add_proc_dout_rd_5
    );
  error_add_proc_dout_0 : FDCE
    port map (
      D => error_add_proc_xor0000(0),
      CE => error_add_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => error_add_proc_dout(0)
    );
  error_add_proc_dout_1 : FDCE
    port map (
      D => error_add_proc_xor0000(1),
      CE => error_add_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => error_add_proc_dout(1)
    );
  error_add_proc_dout_2 : FDCE
    port map (
      D => error_add_proc_xor0000(2),
      CE => error_add_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => error_add_proc_dout(2)
    );
  error_add_proc_dout_3 : FDCE
    port map (
      D => error_add_proc_xor0000(3),
      CE => error_add_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => error_add_proc_dout(3)
    );
  error_add_proc_dout_4 : FDCE
    port map (
      D => error_add_proc_xor0000(4),
      CE => error_add_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => error_add_proc_dout(4)
    );
  error_add_proc_dout_5 : FDCE
    port map (
      D => error_add_proc_xor0000(5),
      CE => error_add_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => error_add_proc_dout(5)
    );
  error_add_proc_dout_6 : FDCE
    port map (
      D => N10,
      CE => error_add_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => error_add_proc_dout(6)
    );
  error_add_proc_code_count_0 : FDCE
    port map (
      D => error_add_proc_code_count_add0000(0),
      CE => error_add_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => error_add_proc_code_count(0)
    );
  error_add_proc_code_count_1 : FDCE
    port map (
      D => error_add_proc_code_count_add0000(1),
      CE => error_add_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => error_add_proc_code_count(1)
    );
  error_add_proc_code_count_2 : FDCE
    port map (
      D => error_add_proc_code_count_add0000(2),
      CE => error_add_proc_and0000,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => error_add_proc_code_count(2)
    );
  error_add_proc_Mrom_mux00007 : LUT3
    generic map(
      INIT => X"81"
    )
    port map (
      I0 => error_add_proc_code_count(0),
      I1 => error_add_proc_code_count(1),
      I2 => error_add_proc_code_count(2),
      O => N10
    );
  encode_proc_Mrom_mux00021 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_in_0_IBUF_8,
      I1 => data_in_1_IBUF_7,
      O => N11
    );
  encode_proc_Mrom_mux00022 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_in_0_IBUF_8,
      I1 => data_in_2_IBUF_6,
      O => N12
    );
  encode_proc_Mrom_mux00023 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_in_1_IBUF_7,
      I1 => data_in_2_IBUF_6,
      O => N13
    );
  decode_proc_bit_count_0 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => decode_proc_mux0003(2),
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => decode_proc_bit_count(0)
    );
  decode_proc_bit_count_1 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => decode_proc_mux0003(1),
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => decode_proc_bit_count(1)
    );
  decode_proc_bit_count_2 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => decode_proc_mux0003(0),
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => decode_proc_bit_count(2)
    );
  decode_proc_data_nd_dly : FDC
    port map (
      D => error_add_proc_dout_rd_5,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => decode_proc_data_nd_dly_11
    );
  decode_proc_syn_0 : FDC
    port map (
      D => decode_proc_mux0004(2),
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => decode_proc_syn(0)
    );
  decode_proc_syn_1 : FDC
    port map (
      D => decode_proc_mux0004(1),
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => decode_proc_syn(1)
    );
  decode_proc_dout_rd : FDC
    port map (
      D => decode_proc_mux0005,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => decode_proc_dout_rd_3
    );
  decode_proc_error_out_0 : FDCE
    port map (
      D => error_add_proc_dout(3),
      CE => decode_proc_state_reg_FFd1_12,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => decode_proc_error_out(0)
    );
  decode_proc_error_out_1 : FDCE
    port map (
      D => error_add_proc_dout(4),
      CE => decode_proc_state_reg_FFd1_12,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => decode_proc_error_out(1)
    );
  decode_proc_error_out_2 : FDCE
    port map (
      D => error_add_proc_dout(5),
      CE => decode_proc_state_reg_FFd1_12,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => decode_proc_error_out(2)
    );
  decode_proc_error_out_3 : FDCE
    port map (
      D => error_add_proc_dout(6),
      CE => decode_proc_state_reg_FFd1_12,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => decode_proc_error_out(3)
    );
  decode_proc_dout_0 : FDCE
    port map (
      D => decode_proc_xor0000(0),
      CE => decode_proc_state_reg_FFd1_12,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => decode_proc_dout(0)
    );
  decode_proc_state_reg_FFd1 : FDC
    port map (
      D => decode_proc_state_reg_FFd1_In,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => decode_proc_state_reg_FFd1_12
    );
  decode_proc_state_reg_FFd2 : FDC
    port map (
      D => decode_proc_state_reg_FFd2_In,
      CLR => aclr_IBUF_1,
      C => clk_BUFGP_0,
      Q => decode_proc_state_reg_FFd2_13
    );
  decode_proc_bit_count_0_Q : LUT3
    generic map(
      INIT => X"AC"
    )
    port map (
      I0 => error_add_proc_dout(5),
      I1 => error_add_proc_dout(4),
      I2 => decode_proc_bit_count(0),
      O => decode_proc_N21
    );
  decode_proc_bit_count_1_f5 : MUXF5
    port map (
      I0 => decode_proc_N21,
      I1 => error_add_proc_dout_6_rt_15,
      S => decode_proc_bit_count(1),
      O => decode_proc_bit_count_1_f5_14
    );
  decode_proc_bit_count_0_1 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => error_add_proc_dout(2),
      I1 => error_add_proc_dout(3),
      I2 => decode_proc_bit_count(0),
      O => decode_proc_N31
    );
  decode_proc_bit_count_0_2 : LUT3
    generic map(
      INIT => X"AC"
    )
    port map (
      I0 => error_add_proc_dout(1),
      I1 => error_add_proc_dout(0),
      I2 => decode_proc_bit_count(0),
      O => decode_proc_N41
    );
  decode_proc_bit_count_1_f5_0 : MUXF5
    port map (
      I0 => decode_proc_N41,
      I1 => decode_proc_N31,
      S => decode_proc_bit_count(1),
      O => decode_proc_bit_count_1_f51
    );
  decode_proc_Mmux_mux0000_f6 : MUXF6
    port map (
      I0 => decode_proc_bit_count_1_f51,
      I1 => decode_proc_bit_count_1_f5_14,
      S => decode_proc_bit_count(2),
      O => decode_proc_mux0000