gumio.c

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// Copyright (c) David Vescovi.  All rights reserved.
// Part of Project DrumStix
// Windows Embedded Developers Interest Group (WE-DIG) community project.
// http://www.we-dig.org
// Copyright (c) Microsoft Corporation.  All rights reserved.
//------------------------------------------------------------------------------
//
//  File:  gumio.c            
//
//  This module sets up Gumstix specific peripheral GPIO.
//
//------------------------------------------------------------------------------
#include "bsp.h"
#include <nkintr.h>
 
//------------------------------------------------------------------------------
// Defines 
//
#define MCMEM0_value	0x0002449D		// Card I-face Common Mem Space socket 0 timing config
#define MCMEM1_value	0x0002449D		// Card I-face Common Mem Space socket 1 timing config
#define MCATT0_value	0x0002449D		// Card I-face Attribute Space socket 0 timing config
#define MCATT1_value	0x0002449D		// Card I-face Attribute Space socket 1 timing config
#define MCIO0_value		0x00014290		// Card I-face I/O Space socket 0 timing config
#define MCIO1_value		0x00014290		// Card I-face I/O Space socket 1 timing config

//------------------------------------------------------------------------------
// Externs
//
 
//------------------------------------------------------------------------------
// Global Variables 
 
//------------------------------------------------------------------------------
// Local Variables 
//

//------------------------------------------------------------------------------
// Local Functions 
//
// Direct HWUART function to GPIO42-45 for auto-handshake support
// with Bluetooth module
static BOOL InitHWUartAF3(void)
{
    volatile GPIO_REG_T *pGPIORegs = (volatile GPIO_REG_T *) OALPAtoVA(PXA255_BASE_REG_PA_GPIO, FALSE);
    volatile CLK_REG_T  *pCLKRegs =  (volatile CLK_REG_T *)  OALPAtoVA(PXA255_BASE_REG_PA_CLK, FALSE);
    volatile UART_REG_T *pUARTRegs = (volatile UART_REG_T *) OALPAtoVA(PXA255_BASE_REG_PA_HWUART, FALSE);

    // Ensure that UART interrupts are turned off.
    //
    pUARTRegs->LCR     = 0x0;    // Clear DLAB.
    pUARTRegs->IER_DLH = 0x0;    // IER_DLH = 0x0.

    // Set the Baud Rate (Divisor low = DEBUG_BAUD_38400).
    // The divisor latches are at offsets 0 and 1, which are 
    // receive/transmit data and ier registers.
    //
    pUARTRegs->LCR         = 0x80;                // Access Divisor.
    pUARTRegs->THR_RBR_DLL = DEBUG_BAUD;		  // Low byte divisor.
    pUARTRegs->IER_DLH     = 0x00;                // High byte divisor.
    pUARTRegs->LCR         = 0x0;                 // Clear DLAB.

    //Setting UART properties to 8N1 
    //
    pUARTRegs->LCR         = 0x3;     // 8 bits, 1 stop, no parity. Also LCR DLAB bit = 0.

    pUARTRegs->IIR_FCR     = 0x01;    // Enable the FIFO.
    pUARTRegs->IIR_FCR     = 0x07;    // Clear Rx,Tx FIFOs.

    // Don't enable UART interrupts - we'll poll for the data.
    //
    pUARTRegs->IER_DLH     = 0x0;  

    // Ensure loop-back test mode is off even though MCR reset value is 0x0. 
    //
    pUARTRegs->MCR         = (UART_MCR_RTS | UART_MCR_AFE);    // UART in auto mode.

	// Configure GPIO pins for HWUART
    // Initialize GPIO pins.
    // Write 0 on GPIO pins 43 and 45 before configuring them as outputs.
    // Note:Pins shared with BTUART (BTUART and HWUART are mutually exclusive)
    pGPIORegs->GPCR1 = (GPIO_43 | GPIO_45);

    // Configure direction of GPIO pins 42 and 44 as input 
    // and GPIO pins 43 and 45 as output.
    //
    pGPIORegs->GPDR1 &= ~( GPIO_42 | GPIO_44); 
    pGPIORegs->GPDR1 |=  ( GPIO_43 | GPIO_45);

	// Configure GPIO pins 42,43,44 and 45 for Alt_fn3.
    pGPIORegs->GAFR1_L |= ( GPIO_42_AF3_HWRXD | GPIO_44_AF3_HWCTS |
                            GPIO_43_AF3_HWTXD | GPIO_45_AF3_HWRTS );

	// Enable the HWUART clock.
	//
	pCLKRegs->CKEN |= CKEN_HWUART ;

    // Enable the UART.
    //
    pUARTRegs->IER_DLH = 0x40;

    return(TRUE);

}

//------------------------------------------------------------------------------
//
//  Function: OEMInitCF
//
//  Initializes the CF socket
//
//------------------------------------------------------------------------------

BOOL OEMInitCF(BOOL dualSlot) 
{
	volatile MEMC_REG_T *pMEMCRegs = (volatile MEMC_REG_T *) OALPAtoVA(PXA255_BASE_REG_PA_MEMC, FALSE);
	volatile GPIO_REG_T *pGPIORegs = (volatile GPIO_REG_T *) OALPAtoVA(PXA255_BASE_REG_PA_GPIO, FALSE);

	// Initialize socket timing
	pMEMCRegs->MCMEM0 = MCMEM0_value;
	pMEMCRegs->MCMEM1 = MCMEM1_value;
	pMEMCRegs->MCATT0 = MCATT0_value;
	pMEMCRegs->MCATT1 = MCATT1_value;
	pMEMCRegs->MCIO0  = MCIO0_value;	
	pMEMCRegs->MCIO1  = MCIO1_value;	

	// Initialize GPIO pins
    //
	// Configure GPIO pins for CF misc functions
	pGPIORegs->GPSR0 =   ( GPIO_8_CFRESET );
	pGPIORegs->GPDR0 |=  ( GPIO_8_CFRESET );
	OALStall(50);
	pGPIORegs->GPCR0 =   ( GPIO_8_CFRESET );

	pGPIORegs->GPDR0 &= ~( GPIO_4_S0_BVD1 | 
						   GPIO_11_S0_nCARD_DETECT |
						   GPIO_26_S0_READY_nIREQ );
	pGPIORegs->GPDR1 &= ~( GPIO_36_S0_BVD2 );

	// Configure GPIO pins for CF Card socket
	// Write 1 on GPIO pins 48-55 before configuring them as outputs.
	pGPIORegs->GPSR1 =   ( GPIO_48 | GPIO_49 | GPIO_50 | GPIO_51 |
						   GPIO_52 | GPIO_53 | GPIO_54 | GPIO_55);

	// Configure direction of GPIO pins 48-55 as output
	// and GPIO pins 56 & 57 as input
	pGPIORegs->GPDR1 |=  ( GPIO_48 | GPIO_49 | GPIO_50 | GPIO_51 |
						   GPIO_52 | GPIO_53 | GPIO_54 | GPIO_55 );
	pGPIORegs->GPDR1 &= ~( GPIO_56 | GPIO_57 ); 

	// Configure GPIO pins for Alt_fnX to support CF cards.
	// assume relevent ALT bits are already preset to 0's.
	pGPIORegs->GAFR1_U |= ( GPIO_48_AF2_nPOE    | GPIO_49_AF2_nPWE |
							GPIO_50_AF2_nPIOR   | GPIO_51_AF2_nPIOW |
							GPIO_52_AF2_nPCE1   | GPIO_53_AF2_nPCE2 |
							GPIO_54_AF2_pSKTSEL | GPIO_55_AF2_nPREG |
							GPIO_56_AF1_nPWAIT  | GPIO_57_AF1_nIOIS16 );

	if (dualSlot)
	{
		pGPIORegs->GPDR0 &= ~( GPIO_18_S1_BVD1 | GPIO_27_S1_READY_nIREQ );
		pMEMCRegs->MECR = MECR_CIT | MECR_NOS;
	}
	else
	{
		pMEMCRegs->MECR = MECR_CIT;
	}

    return(TRUE);
}


//------------------------------------------------------------------------------
//
//  Function: OEMInitMMC
//
//  Initializes the MMC socket
//
//------------------------------------------------------------------------------

BOOL OEMInitMMC(BOOL netMMC) 
{
	volatile GPIO_REG_T *pGPIORegs = (volatile GPIO_REG_T *) OALPAtoVA(PXA255_BASE_REG_PA_GPIO, FALSE);
    volatile CLK_REG_T  *pCLKRegs =  (volatile CLK_REG_T *)  OALPAtoVA(PXA255_BASE_REG_PA_CLK, FALSE);

	// set MMCLK and MMCCS0 high before configuring as output 
	pGPIORegs->GPSR0 =  (GPIO_6 | GPIO_8);
	pGPIORegs->GPDR0 |= (GPIO_6 | GPIO_8);
	// Card Detects as inputs
	pGPIORegs->GPDR0 &= ~( GPIO_22_nCDMMC );
	pGPIORegs->GPDR1 &= ~( GPIO_54_nCDMMC );

	// set pins 6 and 8 to alternate function 1
    pGPIORegs->GAFR0_L |= (GPIO_6_AF1_MMCLK | GPIO_8_AF1_MMCCS0);
 
	if (netMMC)
	{
		// set MMCLK #2 pin for output mode 
		pGPIORegs->GPSR1 = (GPIO_53);
		pGPIORegs->GPDR1 |= (GPIO_53);

		// set pins 53 to alternate function 1
	    pGPIORegs->GAFR1_U |= GPIO_53_AF1_MMCCLK;
	}

	pCLKRegs->CKEN |= CKEN_MMC ;

	return(TRUE);

}


//------------------------------------------------------------------------------
//
//  Function:  OEMInitUart
//
//  Set up a uart.
//
//------------------------------------------------------------------------------

BOOL OEMInitUart(UINT32 UARTPhysAddr)
{
    volatile GPIO_REG_T *pGPIORegs = (volatile GPIO_REG_T *) OALPAtoVA(PXA255_BASE_REG_PA_GPIO, FALSE);
    volatile CLK_REG_T  *pCLKRegs =  (volatile CLK_REG_T *)  OALPAtoVA(PXA255_BASE_REG_PA_CLK, FALSE);
    volatile UART_REG_T *pUARTRegs = (volatile UART_REG_T *) OALPAtoVA(UARTPhysAddr, FALSE);

    // Ensure that UART interrupts are turned off.
    //
    pUARTRegs->LCR     = 0x0;    // Clear DLAB.
    pUARTRegs->IER_DLH = 0x0;    // IER_DLH = 0x0.

    // Set the Baud Rate (Divisor low = DEBUG_BAUD_38400).
    // The divisor latches are at offsets 0 and 1, which are 
    // receive/transmit data and ier registers.
    //
    pUARTRegs->LCR         = 0x80;                // Access Divisor.
    pUARTRegs->THR_RBR_DLL = DEBUG_BAUD;		  // Low byte divisor.
    pUARTRegs->IER_DLH     = 0x00;                // High byte divisor.
    pUARTRegs->LCR         = 0x0;                 // Clear DLAB.

    //Setting UART properties to 8N1 
    //
    pUARTRegs->LCR         = 0x3;     // 8 bits, 1 stop, no parity. Also LCR DLAB bit = 0.

    pUARTRegs->IIR_FCR     = 0x01;    // Enable the FIFO.
    pUARTRegs->IIR_FCR     = 0x07;    // Clear Rx,Tx FIFOs.

    // Don't enable UART interrupts - we'll poll for the data.
    //
    pUARTRegs->IER_DLH     = 0x0;  

    // Ensure loop-back test mode is off even though MCR reset value is 0x0. 
    //
    pUARTRegs->MCR         = 0x0;    // UART is in normal mode.

	// Initialize GPIO pins
    //
    if (UARTPhysAddr == PXA255_BASE_REG_PA_FFUART)
    {
		// Configure GPIO pins for FFUART
		// Write 0 on GPIO pins 39 before configuring them as outputs.
		pGPIORegs->GPCR1 = ( GPIO_39 );

		// Configure direction of GPIO pins 34 as input
		// and GPIO pins 39 as output
		pGPIORegs->GPDR1 &= ~( GPIO_34 ); 
		pGPIORegs->GPDR1 |=  ( GPIO_39 );

		// Configure GPIO pins 34 for Alt_fn1. And pins 39 for Alt_fn2.
		pGPIORegs->GAFR1_L |= ( GPIO_34_AF1_FFRXD | GPIO_39_AF2_FFTXD );

		// Enable the FFUART clock.
		//
		pCLKRegs->CKEN |= CKEN_FFUART ;

    }
    if (UARTPhysAddr == PXA255_BASE_REG_PA_STUART)
    {
		// Configure GPIO pins for STUART
		// Write 0 on GPIO pins 47 before configuring them as outputs.
		pGPIORegs->GPCR1 = ( GPIO_47 );

		// Configure direction of GPIO pins 46 as input
		// and GPIO pins 47 as output
		pGPIORegs->GPDR1 &= ~( GPIO_46 ); 
		pGPIORegs->GPDR1 |=  ( GPIO_47 );

		// Configure GPIO pins 46 for Alt_fn2. And pins 47 for Alt_fn1.
		pGPIORegs->GAFR1_L |= ( GPIO_46_AF2_RXD | GPIO_47_AF1_TXD );

		// Enable the STUART clock.
		//
		pCLKRegs->CKEN |= CKEN_STUART ;

    }
    if (UARTPhysAddr == PXA255_BASE_REG_PA_HWUART)
    {
		// Configure GPIO pins for HWUART
        // Initialize GPIO pins.
	    // Write 0 on GPIO pins 48 and 51 before configuring them as outputs.
	    pGPIORegs->GPCR1 = (GPIO_48 | GPIO_51);

	    // Configure direction of GPIO pins 49 and 50 as input 
	    // and GPIO pins 48 and 51 as output.
        //
	    pGPIORegs->GPDR1 &= ~( GPIO_49 | GPIO_50); 
	    pGPIORegs->GPDR1 |=  ( GPIO_48 | GPIO_51);

		// Configure GPIO pins 48,49,50 and 51 for Alt_fn1.
	    pGPIORegs->GAFR1_U |= ( GPIO_49_AF1_HWRXD | GPIO_50_AF1_HWCTS |
                                GPIO_48_AF1_HWTXD | GPIO_51_AF1_HWRTS );

		// Enable the HWUART clock.