_primary.vhd

arm verilog的相关代码 仅仅供学习使用

library verilog;
use verilog.vl_types.all;
entity D_Bus2Core is
    port(
        in_MEMAccessAddress: in     vl_logic_vector(31 downto 0);
        out_DataCacheBus: inout  vl_logic_vector(31 downto 0);
        in_DataCacheBus : inout  vl_logic_vector(31 downto 0);
        in_MEMAccessRequest: in     vl_logic;
        in_MEMAccessBW  : in     vl_logic;
        in_MEMAccessRW  : in     vl_logic;
        out_DataCacheWait: out    vl_logic;
        wb_ack_i        : in     vl_logic;
        wb_addr_o       : out    vl_logic_vector(31 downto 0);
        wb_cyc_o        : out    vl_logic;
        wb_data_i       : in     vl_logic_vector(31 downto 0);
        wb_data_o       : out    vl_logic_vector(31 downto 0);
        wb_err_i        : in     vl_logic;
        wb_rty_i        : in     vl_logic;
        wb_sel_o        : out    vl_logic_vector(7 downto 0);
        wb_stb_o        : out    vl_logic;
        wb_we_o         : out    vl_logic;
        clk_i           : in     vl_logic;
        rst_i           : in     vl_logic
    );
end D_Bus2Core;