mc8051_top.sap

这是一个基于xilinx平台的8051处理器文件

ap .clock "NONE";
ap .clock_edge "rise";

gi gprbit_11[7:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.i_mc8051_control.i_control_mem.un1_gprbit_11_1_sqmuxa";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi gprbit_12[7:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.i_mc8051_control.i_control_mem.un1_gprbit_12_1_sqmuxa";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi gprbit_13[7:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.i_mc8051_control.i_control_mem.un1_gprbit_13_1_sqmuxa";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi gprbit_14[7:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.i_mc8051_control.i_control_mem.un1_gprbit_14_1_sqmuxa";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi gprbit_15[7:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.i_mc8051_control.i_control_mem.un1_gprbit_15_1_sqmuxa";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi acc[0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.i_mc8051_control.i_control_mem.un1_acc_1_sqmuxa";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi acc[1];
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.i_mc8051_control.i_control_mem.un1_tsel21_8";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi acc[2];
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.i_mc8051_control.i_control_mem.un1_tsel21_3";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi acc[3];
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.i_mc8051_control.i_control_mem.un1_tsel21_6";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi acc[4];
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.i_mc8051_control.i_control_mem.un1_tsel21_7";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi acc[5];
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.i_mc8051_control.i_control_mem.un1_tsel21_2";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi acc[6];
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.i_mc8051_control.i_control_mem.un1_tsel21_5";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi acc[7];
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.i_mc8051_control.i_control_mem.un1_tsel21_4";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi psw[7:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi scon_0[7:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi tcon_0[7:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi sp[7:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

d i_mc8051_core.i_mc8051_alu.i_addsub_core.gen_greater_four.gen_addsub.4.gen_nibble_addsub.i_addsub_cy;

gi un1_cy_i_1[0:5];
ai .rtl_dangling_pins "OUT[0]";


d i_mc8051_core.i_mc8051_alu.i_addsub_core.gen_greater_four.gen_addsub.5.gen_last_addsub.i_addsub_ovcy;

gi un3_v_lresult[2:0];
ai .rtl_dangling_pins "OUT[0]";


gi gen_greater_one.p_addsub_ov.v_result_2[4:0];
ai .rtl_dangling_pins "OUT[1]";


gi v_lresult_2[2:0];
ai .rtl_dangling_pins "OUT[0]";


d i_mc8051_core.gen_mc8051_siu.0.i_mc8051_siu;

gi s_ff0;
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_ff1;
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_rxm13_ff0;
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_txm13_ff0;
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_rxm13_ff1;
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_txm13_ff1;
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi rxdwr_o;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_siu.0.i_mc8051_siu.un1_v_txstep_9_sqmuxa";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_det_ff0;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_siu.0.i_mc8051_siu.un1_s_det_ff0_1_sqmuxa_1";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_det_ff1;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_siu.0.i_mc8051_siu.un1_s_det_ff0_1_sqmuxa_1";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_rb8;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_siu.0.i_mc8051_siu.un1_s_recv_done_2_sqmuxa";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_recv_buf[7:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_siu.0.i_mc8051_siu.un1_v_rxstep_9_sqmuxa_1";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_rxpre_count[5:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_txpre_count[5:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_trans;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_siu.0.i_mc8051_siu.un1_s_trans_1_sqmuxa";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi rxd_o;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_siu.0.i_mc8051_siu.un1_rxd_o_2_sqmuxa";
ai .async_set "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_recv_done;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_siu.0.i_mc8051_siu.un1_s_recv_done_0_sqmuxa";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_rxd_ff0;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_siu.0.i_mc8051_siu.s_rxd_ff0_0_sqmuxa_3";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_rxd_ff1;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_siu.0.i_mc8051_siu.s_rxd_ff0_0_sqmuxa_3";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_rxd_ff2;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_siu.0.i_mc8051_siu.s_rxd_ff0_0_sqmuxa_3";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_tran_done;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_siu.0.i_mc8051_siu.un1_v_txstep_7_sqmuxa_8";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_tran_sh[10:1];
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_siu.0.i_mc8051_siu.un1_rxd_o_2_sqmuxa_2";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_recv_sh[7:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_siu.0.i_mc8051_siu.un1_s_recv_sh_0_sqmuxa_5";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_txdm0;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_siu.0.i_mc8051_siu.un1_s_tran_sh_1_sqmuxa_1";
ai .async_set "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_tran_state[3:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_recv_state[3:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

d i_mc8051_core.gen_mc8051_tmrctr.0.i_mc8051_tmrctr;

gi s_int0_sync[1:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_int1_sync[1:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_t0ff0;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_tmrctr.0.i_mc8051_tmrctr.s_t0ff0_0_sqmuxa";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_t1ff0;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_tmrctr.0.i_mc8051_tmrctr.s_t1ff0_0_sqmuxa";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_t0ff1;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_tmrctr.0.i_mc8051_tmrctr.s_t0ff0_0_sqmuxa";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_t1ff1;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_tmrctr.0.i_mc8051_tmrctr.s_t1ff0_0_sqmuxa";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_t0ff2;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_tmrctr.0.i_mc8051_tmrctr.s_t0ff0_0_sqmuxa";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_t1ff2;
ai .clock "NONE";
ai .clock_edge "rise";
ai .clock_enable "n:i_mc8051_core.gen_mc8051_tmrctr.0.i_mc8051_tmrctr.s_t1ff0_0_sqmuxa";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_pre_count[3:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_tf1;
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_tf0;
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_countl1[7:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_countl0[7:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_counth0[7:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

gi s_counth1[7:0];
ai .clock "NONE";
ai .clock_edge "rise";
ai .async_reset "n:reset";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

d i_mc8051_clockdiv;

gi divcnt[3:0];
ai .clock "NONE";
ai .clock_edge "rise";
gp C;
ap .is_clock 1;
ap .clock "NONE";
ap .clock_edge "rise";

n work mc8051_top struc;

gi i_mc8051_ram;
ai .hdla_expand_thru 1;


gi i_mc8051_rom;
ai .hdla_expand_thru 1;

av .syn_compile_point 1;
av .compile_point_name mc8051_top;