coregen.xml

这是一个基于xilinx平台的8051处理器文件

<?xml version="1.0" encoding="UTF-8"?>
<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
	<Folder label="VERILOG Component Instantiation" treetype="folder">
		<Template label="mc8051_rom" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
mc8051_rom YourInstanceName (
    .addr(addr),
    .clk(clk),
    .dout(dout));

 
		</Template>
		<Template label="mc8051_ram" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
mc8051_ram YourInstanceName (
    .addr(addr),
    .clk(clk),
    .din(din),
    .dout(dout),
    .en(en),
    .we(we));

 
		</Template>
	</Folder>
	<Folder label="VHDL Component Instantiation" treetype="folder">
		<Template label="mc8051_rom" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component mc8051_rom
    port (
    addr: IN std_logic_VECTOR(9 downto 0);
    clk: IN std_logic;
    dout: OUT std_logic_VECTOR(7 downto 0));
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : mc8051_rom
        port map (
            addr =&gt; addr,
            clk =&gt; clk,
            dout =&gt; dout);
 
		</Template>
		<Template label="mc8051_ram" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component mc8051_ram
    port (
    addr: IN std_logic_VECTOR(6 downto 0);
    clk: IN std_logic;
    din: IN std_logic_VECTOR(7 downto 0);
    dout: OUT std_logic_VECTOR(7 downto 0);
    en: IN std_logic;
    we: IN std_logic);
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : mc8051_ram
        port map (
            addr =&gt; addr,
            clk =&gt; clk,
            din =&gt; din,
            dout =&gt; dout,
            en =&gt; en,
            we =&gt; we);
 
		</Template>
	</Folder>
</RootFolder>