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📄 mc8051_top.twr

📁 这是一个基于xilinx平台的8051处理器文件
💻 TWR
字号:
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Release 8.2.03i Trace 
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

D:\Xilinx\bin\nt\trce.exe -ise E:/vtest/xilinx/vhdl8051/mc8051/mc8051.ise
-intstyle ise -e 3 -l 3 -s 4 -xml mc8051_top mc8051_top.ncd -o mc8051_top.twr
mc8051_top.pcf -ucf mc8051_top.ucf

Design file:              mc8051_top.ncd
Physical constraint file: mc8051_top.pcf
Device,speed:             xc3s500e,-4 (PRODUCTION 1.26 2006-08-18)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.

================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 2.967 ns HIGH 50%;

 14 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   2.906ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_i_mc8051_clockdiv_s_clk_pre_c = PERIOD TIMEGRP
        "i_mc8051_clockdiv_s_clk_pre_c" 59 ns HIGH 50%;

 138918079829870610 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is  58.937ns.
--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    2.906|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 138918079829870620 paths, 0 nets, and 12352 connections

Design statistics:
   Minimum period:  58.937ns   (Maximum frequency:  16.967MHz)


Analysis completed Tue Apr 10 11:35:05 2007
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 156 MB



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