mc8051_top_map.mrp

这是一个基于xilinx平台的8051处理器文件

Release 8.2.03i Map I.34
Xilinx Mapping Report File for Design 'mc8051_top'

Design Information
------------------
Command Line   : D:\Xilinx\bin\nt\map.exe -ise
E:/vtest/xilinx/vhdl8051/mc8051/mc8051.ise -intstyle ise -p xc3s500e-fg320-4 -cm
area -pr b -k 4 -c 100 -o mc8051_top_map.ncd mc8051_top.ngd mc8051_top.pcf 
Target Device  : xc3s500e
Target Package : fg320
Target Speed   : -4
Mapper Version : spartan3e -- $Revision: 1.34.32.1 $
Mapped Date    : Tue Apr 10 11:24:59 2007

Design Summary
--------------
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         605 out of   9,312    6%
  Number of 4 input LUTs:           3,188 out of   9,312   34%
Logic Distribution:
  Number of occupied Slices:                        1,795 out of   4,656   38%
    Number of Slices containing only related logic:   1,795 out of   1,795  100%
    Number of Slices containing unrelated logic:          0 out of   1,795    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          3,213 out of   9,312   34%
  Number used as logic:              3,188
  Number used as a route-thru:           9
  Number used for Dual Port RAMs:       16
    (Two LUTs used per Dual Port RAM)
  Number of bonded IOBs:               74 out of     232   31%
  Number of Block RAMs:                2 out of      20   10%
  Number of GCLKs:                     2 out of      24    8%
  Number of MULT18X18SIOs:              1 out of      20    5%

Total equivalent gate count for design:  158,221
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  191 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network
   i_mc8051_core/i_mc8051_control/i_control_mem/s_r0.I_8/SPO has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 7
   more times for the following (max. 5 shown):
   i_mc8051_core/i_mc8051_control/i_control_mem/s_r0.I_7/SPO,
   i_mc8051_core/i_mc8051_control/i_control_mem/s_r0.I_6/SPO,
   i_mc8051_core/i_mc8051_control/i_control_mem/s_r0.I_5/SPO,
   i_mc8051_core/i_mc8051_control/i_control_mem/s_r0.I_4/SPO,
   i_mc8051_core/i_mc8051_control/i_control_mem/s_r0.I_3/SPO
   To see the details of these warning messages, please use the -detail switch.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "clk_ibuf" (output signal=clk_c),
   BUFG symbol "i_mc8051_clockdiv/s_clk_pre_inferred_clock_cb" (output
   signal=s_clk_pre)
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
   1 block(s) removed
  15 block(s) optimized away

Section 5 - Removed Logic
-------------------------
Unused block "i_mc8051_ram/VCC" (ONE) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		i_mc8051_core/gen_mc8051_siu.0.i_mc8051_siu/GND
VCC 		i_mc8051_core/gen_mc8051_siu.0.i_mc8051_siu/VCC
GND 		i_mc8051_core/gen_mc8051_tmrctr.0.i_mc8051_tmrctr/GND
GND 		i_mc8051_core/i_mc8051_alu/gen_divider1.i_comb_divider/GND
VCC 		i_mc8051_core/i_mc8051_alu/gen_divider1.i_comb_divider/VCC
GND 		i_mc8051_core/i_mc8051_alu/gen_multiplier1.i_comb_mltplr/GND
VCC 		i_mc8051_core/i_mc8051_alu/gen_multiplier1.i_comb_mltplr/VCC
GND 		i_mc8051_core/i_mc8051_alu/i_alucore/GND
GND 		i_mc8051_core/i_mc8051_alu/i_alumux/GND
VCC 		i_mc8051_core/i_mc8051_alu/i_alumux/VCC
GND 		i_mc8051_core/i_mc8051_control/i_control_mem/GND
VCC 		i_mc8051_core/i_mc8051_control/i_control_mem/VCC
GND 		i_mc8051_ram/GND