traplog.tlg

这是一个基于xilinx平台的8051处理器文件

@N: CD630 :".\gentmp0a87132":4:7:4:9|Synthesizing work.top.gen 
@N: CD630 :"syng0a87132":123:7:123:13|Synthesizing work.ram_r_w.select_ram 
@W: CD326 :"syng0a87132":1836:12:1836:15|Port spo of entity unisim.ram16x1d is unconnected
@N: CD630 :"d:\Synplicity\fpga_862\lib\xilinx\unisim.vhd":16093:10:16093:17|Synthesizing unisim.ram16x1d.syn_black_box 
Post processing for unisim.ram16x1d.syn_black_box
@W: CD326 :"syng0a87132":1836:12:1836:15|Port spo of entity unisim.ram16x1d is unconnected
@W: CD326 :"syng0a87132":1836:12:1836:15|Port spo of entity unisim.ram16x1d is unconnected
@W: CD326 :"syng0a87132":1836:12:1836:15|Port spo of entity unisim.ram16x1d is unconnected
@W: CD326 :"syng0a87132":1836:12:1836:15|Port spo of entity unisim.ram16x1d is unconnected
@W: CD326 :"syng0a87132":1836:12:1836:15|Port spo of entity unisim.ram16x1d is unconnected
@W: CD326 :"syng0a87132":1836:12:1836:15|Port spo of entity unisim.ram16x1d is unconnected
@W: CD326 :"syng0a87132":1836:12:1836:15|Port spo of entity unisim.ram16x1d is unconnected
Post processing for work.ram_r_w.select_ram
Post processing for work.top.gen
@W: CL159 :"syng0a87132":141:2:141:5|Input OCLK is unused