mc8051_top.par

这是一个基于xilinx平台的8051处理器文件

Release 8.2.03i par I.34
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

LENOVO-41E016C8::  Tue Apr 10 11:25:33 2007

par -w -intstyle ise -ol std -t 1 mc8051_top_map.ncd mc8051_top.ncd
mc8051_top.pcf 


Constraints file: mc8051_top.pcf.
Loading device for application Rf_Device from file '3s500e.nph' in environment D:\Xilinx.
   "mc8051_top" is an NCD, version 3.1, device xc3s500e, package fg320, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)


Device speed data version:  "PRODUCTION 1.26 2006-08-18".


Design Summary Report:

 Number of External IOBs                          74 out of 232    31%

   Number of External Input IOBs                 39

      Number of External Input IBUFs             39
        Number of LOCed External Input IBUFs      2 out of 39      5%


   Number of External Output IOBs                35

      Number of External Output IOBs             35
        Number of LOCed External Output IOBs      8 out of 35     22%


   Number of External Bidir IOBs                  0


   Number of BUFGMUXs                  2 out of 24      8%
   Number of MULT18X18SIOs             1 out of 20      5%
   Number of RAMB16s                   2 out of 20     10%
   Number of Slices                 1795 out of 4656   38%
      Number of SLICEMs               26 out of 2328    1%



Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 

Starting initial Timing Analysis.  REAL time: 9 secs 
Finished initial Timing Analysis.  REAL time: 15 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9902af) REAL time: 18 secs 

Phase 2.7
INFO:Place:834 - Only a subset of IOs are locked. Out of 35 IOs, 8 are locked and 27 are not locked. If you would like
   to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 2 (or more). 
Phase 2.7 (Checksum:1312cfe) REAL time: 19 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 19 secs 

Phase 4.2
......
.............


Phase 4.2 (Checksum:989e5f) REAL time: 37 secs 

Phase 5.30
Phase 5.30 (Checksum:2faf07b) REAL time: 37 secs 

Phase 6.3
Phase 6.3 (Checksum:39386fa) REAL time: 37 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 37 secs 

Phase 8.8
..........................................................................................................................................
..............
.......................................................................................................................
..............
.............
....................................
Phase 8.8 (Checksum:11fee3f) REAL time: 2 mins 11 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 2 mins 12 secs 

Phase 10.18
Phase 10.18 (Checksum:5f5e0f6) REAL time: 2 mins 51 secs 

Phase 11.5
Phase 11.5 (Checksum:68e7775) REAL time: 2 mins 51 secs 

Writing design to file mc8051_top.ncd


Total REAL time to Placer completion: 2 mins 56 secs 
Total CPU time to Placer completion: 2 mins 51 secs 

Starting Router

Phase 1: 12921 unrouted;       REAL time: 3 mins 4 secs 

Phase 2: 12391 unrouted;       REAL time: 3 mins 4 secs 

Phase 3: 3816 unrouted;       REAL time: 3 mins 11 secs 

Phase 4: 3816 unrouted; (1922591)      REAL time: 3 mins 22 secs 

Phase 5: 4995 unrouted; (0)      REAL time: 3 mins 47 secs 

Phase 6: 4995 unrouted; (0)      REAL time: 3 mins 58 secs 

Phase 7: 0 unrouted; (0)      REAL time: 4 mins 57 secs 

Phase 8: 0 unrouted; (847)      REAL time: 5 mins 10 secs 

Phase 9: 0 unrouted; (0)      REAL time: 6 mins 33 secs 

Phase 10: 0 unrouted; (0)      REAL time: 7 mins 10 secs 


Total REAL time to Router completion: 7 mins 43 secs 
Total CPU time to Router completion: 7 mins 33 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|               clk_c | BUFGMUX_X1Y11| No   |    3 |  0.002     |  0.133      |
+---------------------+--------------+------+------+------------+-------------+
|           s_clk_pre |  BUFGMUX_X1Y0| No   |  472 |  0.081     |  0.198      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.171
   The MAXIMUM PIN DELAY IS:                               5.499
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   5.043

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
        6273        4492        1823         309          67           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of
                                            |            |            | Levels | Slack      |errors   
------------------------------------------------------------------------------------------------------
  TS_clk = PERIOD TIMEGRP "clk" 2.967 ns HI | 2.967ns    | 2.906ns    | 1      | 0.061ns    | 0       
  GH 50%                                    |            |            |        |            |         
------------------------------------------------------------------------------------------------------
  TS_i_mc8051_clockdiv_s_clk_pre_c = PERIOD | 59.000ns   | 58.937ns   | 41     | 0.063ns    | 0       
   TIMEGRP         "i_mc8051_clockdiv_s_clk |            |            |        |            |         
  _pre_c" 59 ns HIGH 50%                    |            |            |        |            |         
------------------------------------------------------------------------------------------------------


All constraints were met.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 8 mins 25 secs 
Total CPU time to PAR completion: 8 mins 8 secs 

Peak Memory Usage:  206 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file mc8051_top.ncd



PAR done!