lift.prj

实现简易4层电梯控制核心模块

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.6.2
#-- Project file E:\My Synplyfy\lift\lift.prj
#-- Written on Wed Jul 09 18:53:07 2008


#add_file options
add_file -vhdl -lib work "flift.vhd"
add_file -constraint "lift.sdc"


#implementation: "rev_2"
impl -add rev_2 -type fpga

#device options
set_option -technology CYCLONE
set_option -part EP1C3
set_option -package TC144
set_option -speed_grade -8

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -use_fsm_explorer 1

#map options
set_option -frequency auto
set_option -run_prop_extract 1
set_option -fanout_limit 30
set_option -disable_io_insertion 0
set_option -verification_mode 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 1
set_option -no_sequential_opt 0
set_option -fixgatedclocks 0
set_option -quartus_version 6.0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#VIF options
set_option -write_vif 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_2/flift.vqm"

#
#implementation attributes

set_option -vlog_std v2001
set_option -project_relative_includes 1

#par_1 attributes
set_option -job par_1 -add par
set_option -job par_1 -option run_backannotation 0
impl -active "rev_2"