lift.sdc

实现简易4层电梯控制核心模块

# Synplicity, Inc. constraint file
# E:\My Synplyfy\lift\lift.sdc
# Written on Wed Jul 09 18:52:46 2008
# by Synplify Pro, Synplify Pro 8.6.2 Scope Editor

#
# Collections
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#
# Clocks
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define_clock           -virtual -name {CLK}  -freq 100.000 -clockgroup default_clkgroup_0

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# Clock to Clock
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# Inputs/Outputs
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define_input_delay               -default -route 2.00
define_output_delay              -default -route 2.00
define_output_delay -disable     {DOORLIGHT}
define_input_delay -disable      {DOWN2}
define_input_delay -disable      {DOWN3}
define_input_delay -disable      {DOWN4}
define_input_delay -disable      {DOWNLIGHT[4:1]}
define_output_delay -disable     {DOWNLIGHT[4:1]}
define_output_delay -disable     {POSITION[2:0]}
define_input_delay -disable      {RESET}
define_input_delay -disable      {STOP1}
define_input_delay -disable      {STOP2}
define_input_delay -disable      {STOP3}
define_input_delay -disable      {STOP4}
define_input_delay -disable      {STOPLIGHT[4:1]}
define_output_delay -disable     {STOPLIGHT[4:1]}
define_output_delay -disable     {UDSIG}
define_input_delay -disable      {UP1}
define_input_delay -disable      {UP2}
define_input_delay -disable      {UP3}
define_input_delay -disable      {UPLIGHT[4:1]}
define_output_delay -disable     {UPLIGHT[4:1]}

#
# Registers
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# Multicycle Path
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# False Path
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# Path Delay
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# Attributes
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# I/O standards
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# Compile Points
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# Other Constraints
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