flift.srs

实现简易4层电梯控制核心模块

#
#
#
# Created by Synplify VHDL Compiler version 3.6t, Build 206R from Synplicity, Inc.
# Copyright 1994-2006 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Mon Jul 14 14:46:36 2008
#
#
#OPTIONS:"|-infer_seqShift|-primux|-fixsmult|-nram|-divnmod|-autosm|-fid2|-sharing|on|-encrypt|-dfltencoding|onehot|-ui|-lite|-pro|-ram|-ignore_undefined_lib|-ll|2000|-lib|work"
#CUR:"D:\\Program Files\\Synplicity\\fpga_862\\bin\\c_vhdl.exe":1155035930
#CUR:"D:\\Program Files\\Synplicity\\fpga_862\\lib\\vhd\\location.map":1150356088
#CUR:"D:\\Program Files\\Synplicity\\fpga_862\\lib\\vhd\\std.vhd":1144223808
#CUR:"D:\\Program Files\\Synplicity\\fpga_862\\lib\\vhd\\std.vhd":1144223808
#CUR:"D:\\Program Files\\Synplicity\\fpga_862\\lib\\vhd\\std.vhd":1144223808
#CUR:"E:\\My Synplyfy\\lift\\flift.vhd":1216017994
#CUR:"E:\\My Synplyfy\\lift\\flift.vhd":1216017994
#CUR:"E:\\My Synplyfy\\lift\\flift.vhd":1216017994
#CUR:"E:\\My Synplyfy\\lift\\flift.vhd":1216017994
#CUR:"E:\\My Synplyfy\\lift\\flift.vhd":1216017994
#CUR:"E:\\My Synplyfy\\lift\\flift.vhd":1216017994
#CUR:"D:\\Program Files\\Synplicity\\fpga_862\\lib\\vhd\\std1164.vhd":927285456
#CUR:"D:\\Program Files\\Synplicity\\fpga_862\\lib\\vhd\\std1164.vhd":927285456
#CUR:"D:\\Program Files\\Synplicity\\fpga_862\\lib\\vhd\\std1164.vhd":927285456
#CUR:"D:\\Program Files\\Synplicity\\fpga_862\\lib\\vhd\\arith.vhd":1035356678
#CUR:"D:\\Program Files\\Synplicity\\fpga_862\\lib\\vhd\\arith.vhd":1035356678
#CUR:"D:\\Program Files\\Synplicity\\fpga_862\\lib\\vhd\\arith.vhd":1035356678
#CUR:"D:\\Program Files\\Synplicity\\fpga_862\\lib\\vhd\\unsigned.vhd":1068614572
#CUR:"D:\\Program Files\\Synplicity\\fpga_862\\lib\\vhd\\unsigned.vhd":1068614572
#CUR:"D:\\Program Files\\Synplicity\\fpga_862\\lib\\vhd\\unsigned.vhd":1068614572
f "D:\Program Files\Synplicity\fpga_862\lib\vhd\std.vhd"; # file 0
af .is_vhdl 1;
f "E:\My Synplyfy\lift\flift.vhd"; # file 1
af .is_vhdl 1;
f "D:\Program Files\Synplicity\fpga_862\lib\vhd\std1164.vhd"; # file 2
af .is_vhdl 1;
f "D:\Program Files\Synplicity\fpga_862\lib\vhd\arith.vhd"; # file 3
af .is_vhdl 1;
f "D:\Program Files\Synplicity\fpga_862\lib\vhd\unsigned.vhd"; # file 4
af .is_vhdl 1;
@E
@ 
ftell;
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;

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