flift.tlg

来自「实现简易4层电梯控制核心模块」· TLG 代码 · 共 28 行

@N: CD630 :"E:\My Synplyfy\lift\flift.vhd":6:7:6:11|Synthesizing work.flift.behav 
@N: CD231 :"E:\My Synplyfy\lift\flift.vhd":18:16:18:17|Using onehot encoding for type state_type (stopon1="1000000000")
@W: CG296 :"E:\My Synplyfy\lift\flift.vhd":26:0:26:6|Incomplete sensitivity list - assuming completeness
@W: CG290 :"E:\My Synplyfy\lift\flift.vhd":28:4:28:6|Referenced variable rst is not in sensitivity list
@W: CD604 :"E:\My Synplyfy\lift\flift.vhd":138:2:138:14|OTHERS clause is not synthesized 
Post processing for work.flift.behav
@W: CL112 :"E:\My Synplyfy\lift\flift.vhd":40:1:40:2|Feedback mux created for signal UDSIG. Did you forget the set/reset assignment for this signal?
@W: CL112 :"E:\My Synplyfy\lift\flift.vhd":40:1:40:2|Feedback mux created for signal pos[2:0]. Did you forget the set/reset assignment for this signal?
@W: CL112 :"E:\My Synplyfy\lift\flift.vhd":40:1:40:2|Feedback mux created for signal POSITION[2:0]. Did you forget the set/reset assignment for this signal?
@W: CL112 :"E:\My Synplyfy\lift\flift.vhd":40:1:40:2|Feedback mux created for signal DOORLIGHT. Did you forget the set/reset assignment for this signal?
@W: CL190 :"E:\My Synplyfy\lift\flift.vhd":145:1:145:2|Optimizing register bit DOWNLIGHT(1) to a constant 0
@W: CL190 :"E:\My Synplyfy\lift\flift.vhd":145:1:145:2|Optimizing register bit UPLIGHT(4) to a constant 0
@W: CL169 :"E:\My Synplyfy\lift\flift.vhd":145:1:145:2|Pruning Register DOWNLIGHT(1)  
@W: CL169 :"E:\My Synplyfy\lift\flift.vhd":145:1:145:2|Pruning Register UPLIGHT(4)  
@N: CL201 :"E:\My Synplyfy\lift\flift.vhd":40:1:40:2|Trying to extract state machine for register STATE
Extracted state machine for register STATE
State machine has 10 reachable states with original encodings of:
   0000000001
   0000000010
   0000000100
   0000001000
   0000010000
   0000100000
   0001000000
   0010000000
   0100000000
   1000000000