flift.tcl

实现简易4层电梯控制核心模块

# Run with quartus_sh -t <x_cons.tcl>

# Global assignments 
set_global_assignment -name TOP_LEVEL_ENTITY "|FLIFT"
set_global_assignment -name FAMILY "CYCLONE"
set_global_assignment -name DEVICE "EP1C3T144C8"
set_global_assignment -section_id FLIFT -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "SYNPLIFY"
set_global_assignment -section_id eda_design_synthesis -name EDA_USE_LMF synplcty.lmf
set_global_assignment -name TAO_FILE "myresults.tao"
set_global_assignment -name SOURCES_PER_DESTINATION_INCLUDE_COUNT "1000" 
set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS "OFF"
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS "OFF"
set_global_assignment -name REMOVE_DUPLICATE_LOGIC "OFF"
# set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
#set_global_assignment -name EDA_RESYNTHESIS_TOOL "AMPLIFY"

# Clock assignments 

create_base_clock CLK_setting -fmax 1.0mhz -duty_cycle 50.00 -target CLK 

set_output_delay -to UPLIGHT\[1\] 2.000ns -clk_ref |Q0
set_output_delay -to UPLIGHT\[2\] 2.000ns -clk_ref |Q0
set_output_delay -to UPLIGHT\[3\] 2.000ns -clk_ref |Q0
set_output_delay -to DOWNLIGHT\[2\] 2.000ns -clk_ref |Q0
set_output_delay -to DOWNLIGHT\[3\] 2.000ns -clk_ref |Q0
set_output_delay -to DOWNLIGHT\[4\] 2.000ns -clk_ref |Q0
set_output_delay -to STOPLIGHT\[1\] 2.000ns -clk_ref |Q0
set_output_delay -to STOPLIGHT\[2\] 2.000ns -clk_ref |Q0
set_output_delay -to STOPLIGHT\[3\] 2.000ns -clk_ref |Q0
set_output_delay -to STOPLIGHT\[4\] 2.000ns -clk_ref |Q0
set_output_delay -to UDSIG 2.000ns -clk_ref |Q3
set_output_delay -to POSITION\[0\] 2.000ns -clk_ref |Q3
set_output_delay -to POSITION\[1\] 2.000ns -clk_ref |Q3
set_output_delay -to POSITION\[2\] 2.000ns -clk_ref |Q3
set_output_delay -to DOORLIGHT 2.000ns -clk_ref |Q3
set_input_delay -to RST 2.000ns -clk_ref |Q3
set_input_delay -to UP1 2.000ns -clk_ref |Q0
set_input_delay -to UP2 2.000ns -clk_ref |Q0
set_input_delay -to UP3 2.000ns -clk_ref |Q0
set_input_delay -to DOWN2 2.000ns -clk_ref |Q0
set_input_delay -to DOWN3 2.000ns -clk_ref |Q0
set_input_delay -to DOWN4 2.000ns -clk_ref |Q0
set_input_delay -to STOP1 2.000ns -clk_ref |Q0
set_input_delay -to STOP2 2.000ns -clk_ref |Q0
set_input_delay -to STOP3 2.000ns -clk_ref |Q0
set_input_delay -to STOP4 2.000ns -clk_ref |Q0

# False path constraints 

# Multicycle constraints 

# Path delay constraints