flift.srr

实现简易4层电梯控制核心模块

#Build: Synplify Pro 8.6.2, Build 013R, Jun  5 2006
#install: D:\Program Files\Synplicity\fpga_862
#OS: Windows XP 5.1
#Hostname: A6FF1236EE004A2

#Mon Jul 14 14:46:42 2008

$ Start of Compile
#Mon Jul 14 14:46:42 2008

Synplicity VHDL Compiler, version 3.6t, Build 206R, built Aug  8 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@N: CD720 :"D:\Program Files\Synplicity\fpga_862\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"E:\My Synplyfy\lift\flift.vhd":6:7:6:11|Top entity is set to FLIFT.
VHDL syntax check successful!

Compiler output is up to date.  No re-compile necessary

@N: CD630 :"E:\My Synplyfy\lift\flift.vhd":6:7:6:11|Synthesizing work.flift.behav 
@N: CD231 :"E:\My Synplyfy\lift\flift.vhd":18:16:18:17|Using onehot encoding for type state_type (stopon1="1000000000")
@W: CG296 :"E:\My Synplyfy\lift\flift.vhd":26:0:26:6|Incomplete sensitivity list - assuming completeness
@W: CG290 :"E:\My Synplyfy\lift\flift.vhd":28:4:28:6|Referenced variable rst is not in sensitivity list
@W: CD604 :"E:\My Synplyfy\lift\flift.vhd":138:2:138:14|OTHERS clause is not synthesized 
Post processing for work.flift.behav
@W: CL112 :"E:\My Synplyfy\lift\flift.vhd":40:1:40:2|Feedback mux created for signal UDSIG. Did you forget the set/reset assignment for this signal?
@W: CL112 :"E:\My Synplyfy\lift\flift.vhd":40:1:40:2|Feedback mux created for signal pos[2:0]. Did you forget the set/reset assignment for this signal?
@W: CL112 :"E:\My Synplyfy\lift\flift.vhd":40:1:40:2|Feedback mux created for signal POSITION[2:0]. Did you forget the set/reset assignment for this signal?
@W: CL112 :"E:\My Synplyfy\lift\flift.vhd":40:1:40:2|Feedback mux created for signal DOORLIGHT. Did you forget the set/reset assignment for this signal?
@W: CL190 :"E:\My Synplyfy\lift\flift.vhd":145:1:145:2|Optimizing register bit DOWNLIGHT(1) to a constant 0
@W: CL190 :"E:\My Synplyfy\lift\flift.vhd":145:1:145:2|Optimizing register bit UPLIGHT(4) to a constant 0
@W: CL169 :"E:\My Synplyfy\lift\flift.vhd":145:1:145:2|Pruning Register DOWNLIGHT(1)  
@W: CL169 :"E:\My Synplyfy\lift\flift.vhd":145:1:145:2|Pruning Register UPLIGHT(4)  
@N: CL201 :"E:\My Synplyfy\lift\flift.vhd":40:1:40:2|Trying to extract state machine for register STATE
Extracted state machine for register STATE
State machine has 10 reachable states with original encodings of:
   0000000001
   0000000010
   0000000100
   0000001000
   0000010000
   0000100000
   0001000000
   0010000000
   0100000000
   1000000000
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Jul 14 14:46:42 2008

###########################################################]
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Synplicity Altera Technology Mapper, Version 8.6.2, Build 027R, Built Aug 11 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Version 8.6.2
Reading constraint file: E:\My Synplyfy\lift\lift.sdc
Adding property syn_reference_clock1, value "CLK,r=0.0,f=5.0,u=0.0,p=10.0,clockgroup=default_clkgroup_0,rd=0.0,fd=0.0,v=1" to view:work.FLIFT(behav)
Adding property syn_input_delay1, value "r=0.0,f=0.0,rs=0.0,fs=0.0,improve=0,route=2.00,ref=*" to view:work.FLIFT(behav)
Adding property syn_output_delay2, value "r=0.0,f=0.0,rs=0.0,fs=0.0,improve=0,route=2.00,ref=*" to view:work.FLIFT(behav)
Reading constraint file: E:\My Synplyfy\lift\rev_2\flift_fsm.sdc
@N|Using encoding styles selected by FSM Explorer.
Data created on Wed Jul 09 18:53:21 2008
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
Adding property syn_encoding in cell FLIFT, value "gray", to instance STATE[0:9]


@W: BN132 :"e:\my synplyfy\lift\flift.vhd":40:1:40:2|Removing sequential instance CLEARDN,  because it is equivalent to instance CLEARUP
@N: MT204 |Because following clock(s) are defined in SDC file, Autoconstrain mode is TURNED OFF
@N: FA211 |CLK   
RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 21MB peak: 22MB)
Encoding state machine work.FLIFT(behav)-STATE[0:9]
original code -> new code
   0000000001 -> 0000
   0000000010 -> 0001
   0000000100 -> 0011
   0000001000 -> 0010
   0000010000 -> 0110
   0000100000 -> 0111
   0001000000 -> 0101
   0010000000 -> 0100
   0100000000 -> 1100
   1000000000 -> 1101

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 22MB peak: 23MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 22MB peak: 23MB)

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 47MB peak: 49MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 47MB peak: 49MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 47MB peak: 49MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 48MB peak: 49MB)

Finished technology mapping (Time elapsed 0h:00m:02s; Memory used current: 53MB peak: 54MB)
@N: MF197 |Retiming summary : 0 registers retimed to 0 

		#####  BEGIN RETIMING REPORT  #####

Retiming summary : 0 registers retimed to 0

Original and Pipelined registers replaced by retiming :
		None

New registers created by retiming :
		None


		#####   END RETIMING REPORT  #####


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:02s; Memory used current: 53MB peak: 54MB)

Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 53MB peak: 54MB)
@N: BN191 |Writing property annotation file E:\My Synplyfy\lift\rev_2\flift.tap.

Writing Analyst data base E:\My Synplyfy\lift\rev_2\flift.srm
@N: BN225 |Writing default property annotation file E:\My Synplyfy\lift\rev_2\flift.map.
Writing Verilog Netlist and constraint files
Writing .vqm output for Quartus
Writing Cross reference file for Quartus to E:\My Synplyfy\lift\rev_2\flift.xrf
Found clock FLIFT|CLK with period 1000.00ns 
Found clock FLIFT|Q_derived_clock[3] with period 1000.00ns 
Found clock FLIFT|Q_derived_clock[0] with period 1000.00ns 
All Input Ports in the design have input constraint of 2.00ns 
All Output Ports in the design have output constraint of 2.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Jul 14 14:46:47 2008
#


Top view:               FLIFT
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    E:\My Synplyfy\lift\lift.sdc
                       E:\My Synplyfy\lift\rev_2\flift_fsm.sdc
                       
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 994.387

                             Requested     Estimated     Requested     Estimated                 Clock                        Clock                
Starting Clock               Frequency     Frequency     Period        Period        Slack       Type                         Group                
---------------------------------------------------------------------------------------------------------------------------------------------------
CLK                          100.0 MHz     NA            10.000        NA            NA          virtual                      default_clkgroup_0   
FLIFT|CLK                    1.0 MHz       178.2 MHz     1000.000      5.613         998.915     inferred                     Autoconstr_clkgroup_0
FLIFT|Q_derived_clock[0]     1.0 MHz       178.2 MHz     1000.000      5.613         994.387     derived (from FLIFT|CLK)     Autoconstr_clkgroup_0
FLIFT|Q_derived_clock[3]     1.0 MHz       178.2 MHz     1000.000      5.613         994.495     derived (from FLIFT|CLK)     Autoconstr_clkgroup_0